An Automated Ecosystem for Home and Garden
Who doesn’t love a smart garden?
Who doesn’t love a smart garden?
Helping solve communication issues with the chipKIT Cmod.
What are we talking about when we say the Design Edition of Vivado is device-locked or node-locked?
How fast can the thing go? Use this emulated speedometer project to find out!
Making a robot with a ZedBoard.
A practical guide to making a digital filter for processing audio signals on the ZYBO.
Join one of our upcoming workshops in India!
Digilent and Beti Bilisim, our distributor in Turkey, are happy to announce a joint workshop at Gazi University in Ankara, on September 12, 2015
How and why you’d convert UCF files to XDC files.
Interfacing with eyes by using an iris recognition program with the ZYBO.
A point of confusion for a lot of people new to FPGA design is the constraints file. People are used to just writing code and having it work. However, in FPGA design we have to specify what hardware is being used.
Remember Etch-a-Sketch? Well, here’s a chance to play an updated version!
Software Defined Radio (SDR) is a radio communication system that performs many traditional radio functions in software instead of dedicated hardware circuits. Tasks such as filtering, modulation, demodulation, signal generation, …
Most students do not struggle with equations. They struggle with understanding what those equations actually do. In many learning environments, students define a system, run a process, and then interpret …
If you’re choosing between an FPGA and a SoC, the real question is not which one is “better.” It’s which one fits the job in front of you. Here is …
You open a Verilog example, launch Vivado for the first time, or start reading for a digital design course, and one term keeps showing up: RTL. It usually appears as …