JTAG HS3 Resource Center

Welcome to the resource center for the JTAG HS3!

Here you will find all the reference materials that Digilent has created for the JTAG HS3, as well as links to any external content we have tracked down. If you are interested in purchasing the JTAG HS3, visit the product page on our main website: JTAG HS3

The JTAG HS3 is the newest member of our family of affordable high-speed Xilinx® FPGA programming solutions. The HS3 builds on the successful JTAG HS1 by adding an open drain buffer to pin 14 allowing for the debugging of Xilinx Zynq™-SOC processors. It can be attached to target boards using Xilinx's 2×7 2 mm programming header, and is compatible with all Xilinx tools, including iMPACT™, ChipScope™, and EDK.

When connected to a PC via a standard A to micro-USB cable, the JTAG HS3 receives its power from USB and can be recognized as a Digilent programming cable, even if the HS3 is not attached to the target board. The JTAG bus can be shared with other devices as the HS3's signals are held in high-impedance, except when actively driven during programming. The HS3 is small and light, allowing it to be held firmly in place by the system board connector.

NOTE: This cable is not needed for Digilent FPGA boards as our boards are designed with this functionality natively.

This is a unique programming header and is not compatible with the 1×6 MTE Digilent JTAG Connector.

• Schematic – Schematic currently unavailable, please see the reference manual for product detail
• Reference Manual – Wiki PDF
  • Technical description of the JTAG HS3 and all of its features. The Wiki may contain more up-to-date information than the PDF.
• Sell Sheet – PDF

• HTC: 8473301180
• ECCN: EAR99