Nexys A7 XADC Demo
This project is a Vivado demo using the Nexys A7-100T's analog-to-digital converter circuitry, switches, LEDs, and seven-segment display, written in Verilog. When programmed onto the board, voltage levels between 0 and 1 Volt are read off of the JXADC header. The 16 User LEDs increment from right to left as the voltage difference between the selected channel's pins gets larger. The seven-segment display shows the voltage difference between the selected channel's pins in volts. SW0 and SW1 select which XADC channel is displayed.
See the Nexys A7's Reference Manual for more information about how the Artix 7 FPGA's XADC is connected to header JXADC.
- Nexys A7 with a MicroUSB Programming Cable
- Vivado installation compatible with the latest release of this demo (2022.1)
- See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
- Wires, Breadboard and a Circuit to Test
Download and Usage Instructions
The following releases of this demo can be used with instructions found in the corresponding READMEs in order to run the demo.
Releases are only compatible with the version of the Xilinx tools specified in the release version number. In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.
Note: The latest release tags for each variant and branch are highlighted in green.
|Board Variant||Release Tag||Release Downloads||Setup Instructions|
|Nexys A7-100T||100T/XADC/2022.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/XADC/2022.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-100T||100T/XADC/2021.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/XADC/2021.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-100T||100T/XADC/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/XADC/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys-A7-100T||v2018.2-1||Release ZIP downloads||Github README|
|Nexys A7-50T||v2018.2-1||Release ZIP downloads||Github README|
Note for Advanced Users: All demos for the Nexys A7 are provided through the Nexys-A7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.
Instructions on the use of the latest release can be found in this dropdown:
- Using the Latest Release
Note: This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.
Important: These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.
First, download and extract the '*.xpr.zip' file from the demo release page, linked above.
- Open a Vivado Project from a Release
Select the dropdown corresponding to your operating system, below.
- Build a Vivado Project
Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.
Generate a Bitstream
In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.
This starts with Synthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.
Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.
The Bitstream Generator generates the final output file needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.
Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop-up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click Cancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.
- Set up the Nexys A7
Plug the Nexys A7 into the computer using the microUSB cable. The circuit and wires can be attached after the demo is already running.
- Program a Bitstream onto an FPGA Board
Vivado's Hardware Manager can be opened by clicking on Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of the Vivado window.
The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to the Open Hardware Target wizard click the link in the green banner near the top of the window. From the drop-down that opens, select .
Once the wizard opens, click Next.
The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the Host Name and Port fields.
Click Next to continue.
This screen gives a list of devices connected to the hardware server. If there is only one connected it will be the only device shown.
Click Next to continue.
The final screen shows a summary of the options selected in the wizard. Verify the information and click Finish. The board is now connected to the hardware server.
To program the device with the bit file generated earlier, either click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens, select the device to program (Example: ) and the following window will open:
The Bitstream File field should be automatically filled in with the bit file generated earlier. If not, click the button at the right end of the field and navigate to
<Project Directory>/<Project Name>.runs/impl_1/ and select the bit file (Example: ). Now click Program. This will connect to the board, clear the current configuration, and program it using the new bit file.
At this point, the demo is now running on your board. Refer to the Description and Functionality sections of this document for more information on what it does.
1. LEDs and Switches
The demo reads analog data from each enabled XADC channel (set using sw0 and sw1). The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases. The switch selections for each channel can be seen in the table below:
|Channel||Pin||SW0 / SW1 Positions|
|AD2P/N||XA3||Down / Down|
|AD3P/N||XA1||Up / Down|
|AD10P/N||XA2||Down / Up|
|AD11P/N||XA4||Up / Up|
2. Setting up the Circuit
As seen in the image to the right, this demo was tested using a resistor ladder to show the different brightness values the demo puts out. This demo can be used to measure any voltage between 0 and 1 volt. The circuit uses a chain of eight 1KOhm resistors in series tied to the 3V3 and GND pins of the XADC header to create these voltages.
All materials related to the use of the Nexys A7 can be found on its Resource Center.
For a walkthrough of the process of creating a simple HDL project in Vivado, see Getting Started with Vivado for Hardware-Only Designs. Information on important parts of the GUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found there.
For technical support, please visit the FPGA section of the Digilent Forum.