Nexys A7 OOB Demo
This project is a Vivado demo using the Nexys A7-100T's switches, LEDs, pushbuttons, RGB LEDS, seven-segment display, VGA connector, USB HID Host port, PWM audio output, PDM microphone, 3-axis accelerometer and the temperature sensor written in VHDL. When programmed onto the board, all sixteen of the switches are tied to their corresponding LEDs. Every time a switch is toggled, the LED directly above it will toggle with it. The seven-segment display runs a constant snake pattern.
The two RGB LEDs are initially set to smoothly change from red to green, then green to blue, then blue to red. The table below describes how the D-pad buttons affects the RGB LEDs and the microphone. Once the audio recording is started with the BTNU button the data is taken from the omni-directional microphone and stored into the DDR2 memory. While recording audio the LEDs will light up from left to right. After about 5 seconds the recording stops and the audio will be read from DDR2 memory and played through the headphone jack (labeled mono audio out). Afterwhich the LEDs will turn off from right to left.
The VGA displays a Digilent / Analog Devices logo, the mouse cursor connected by the usb HID Host port, the audio signal from the microphone, the x , y and z data from the Accelerometer, the FPGA temperature and the value of the RGB componnents. The VGA is only displayed in 1280×1024 resolution.
Additional information on how this demo can be used can be found in appropriate READMEs, linked below.
- Arty Z7 with a MicroUSB Programming Cable (and external Power Supply)
- Vivado and Vitis installations compatible with the latest release of this demo (2022.1)
- See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
- Serial Terminal application to receive messages printed by the demo
- See Installing and Using a Terminal Emulator for more information.
- Headphones or Speakers with 3.5mm Audio Jack
- Monitor with a VGA Port
- VGA Cable
- USB Mouse
Download and Usage Instructions
The following releases of this demo can be used with instructions found in the corresponding READMEs in order to run the demo.
Releases are only compatible with the version of the Xilinx tools specified in the release version number. In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.
The latest release version for this demo is highlighted in green.
Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.
|Board Variant||Release Tag||Release Downloads||Setup Instructions|
|Nexys A7-100T||100T/OOB/2022.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/OOB/2022.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-100T||100T/OOB/2021.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/OOB/2021.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-100T||100T/OOB/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-50T||50T/OOB/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Nexys A7-100T||v2018.2-1||Release ZIP downloads||Github README|
|Nexys A7-50T||v2018.2-1||Release ZIP downloads||Github README|
Note for Advanced Users: All demos for the Nexys A7 are provided through the Nexys-A7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.
Instructions on the use of the latest release can be found in this dropdown:
- Using the Latest Release
Note: This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.
Important: These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.
First, download and extract the '*.xpr.zip' file from the demo release page, linked above.
- Open a Vivado Project from a Release
Select the dropdown corresponding to your operating system, below.
- Build a Vivado Project
Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.
Generate a Bitstream
In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.
This starts with Synthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.
Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.
The Bitstream Generator generates the final output file needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.
Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop-up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click Cancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.
- Set up the Nexys A7
Plug the microUSB programming cable into the Nexys A7's PROG/UART port, the VGA cable into the VGA port (and into the monitor), and the headphones or speaker into the MONO AUDIO OUT port.
- Program a Bitstream onto an FPGA Board
Vivado's Hardware Manager can be opened by clicking on Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of the Vivado window.
The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to the Open Hardware Target wizard click the link in the green banner near the top of the window. From the drop-down that opens, select .
Once the wizard opens, click Next.
The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the Host Name and Port fields.
Click Next to continue.
This screen gives a list of devices connected to the hardware server. If there is only one connected it will be the only device shown.
Click Next to continue.
The final screen shows a summary of the options selected in the wizard. Verify the information and click Finish. The board is now connected to the hardware server.
To program the device with the bit file generated earlier, either click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens, select the device to program (Example: ) and the following window will open:
The Bitstream File field should be automatically filled in with the bit file generated earlier. If not, click the button at the right end of the field and navigate to
<Project Directory>/<Project Name>.runs/impl_1/ and select the bit file (Example: ). Now click Program. This will connect to the board, clear the current configuration, and program it using the new bit file.
At this point, the demo is now running on your board. Refer to the Description and Functionality sections of this document for more information on what it does.
1. Using the Switches with LEDs
2. Seven Segment Display
The 7-Segment display runs a constant snake pattern. There is no way to change this pattern with the Nexys A7 I/O.
3. Tri-color LEDs and Push Buttons
The two tri-color LEDs are initially set to gradually change from red to green, then green to blue, then back to red. If the user pushes btnR, the LEDs are set to blue. If the user pushes btnC, the LEDs are set to green. If the user pushes btnL, the LEDs are set to red. Finally if the user pushes btnD, the LEDs return to their gradual change loop. If the user keeps pushing btnD, both LEDs will be isolated then both will be turned off.
4. Audio Recorder
If the user pushes btnU, an audio recording is started and data is taken from the omni-directional microphone. The data is stored into the DDR2 memory. While the recorder is recording, the LEDs will light up from left to right. After about five seconds, the audio will be read from DDR2 memory and played through the headphone jack (labeled mono audio out). LEDs will turn off from right to left.
5. VGA Output and Mouse Control
When the demo is connected to a VGA display, the following is displayed at a 1280×1024 resolution:
- A Digilent logo
- A mouse cursor, if a USB mouse is connected to the board when the project is started
- The audio signal from the onboard ADMP421 Omnidirectional Microphone
- A small square representing the X and Y acceleration data from the ADXL362 onboard >Accelerometer.The square moves according the Nexys4 board position. Note that the X and Y axes on the board are exchanged due to the accelerometer layout on the Nexys4 board.The accelerometer display also displays the acceleration magnitude, calculated asSQRT( X^2 + Y^2 +Z^2), where X, Y and Z represent the acceleration value on the respective axes
- The FPGA temperature, the onboard ADT7420 temperature sensor temperature value and the accelerometer temperature value
- The value of the R, G and B color components sent to the RGB LEDs LD16 and LD17
All materials related to the use of the Nexys A7 can be found on its Resource Center.
For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado and Vitis for Baremetal Software Projects. Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.
For technical support, please visit the FPGA section of the Digilent Forum.