Nexys Video - Getting Started with Microblaze Servers
Note:The Nexys Video uses a Gigabit Ethernet module which requires the TEMAC IP that is not contained in the Vivado Webpack. In order to complete this tutorial, you must either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following this guide.
This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the Getting Started with Microblaze guide by making use of the on-board Ethernet port and GPIOs for the Nexys Video FPGA board.
At the end of this tutorial you will have a comprehensive hardware design for Nexys Video that makes use of various Hardware ports on the Nexys Video which are managed by the Microblaze Softcore Processor block.
- Familiarity with Vivado
- This experience can be found by walking through our “Getting Started with Vivado” guide.
- Nexys Video FPGA Board
- 2 Micro USB Cables
- For UART communication and JTAG programming.
- Ethernet Cable
- Xilinx Vivado with the SDK package.
- Follow this Wiki guide: Installing Vivado on how to install and activate Vivado.
- TEMAC IP license installed
- Follow this Wiki guide: Installing the 120 Day Evaluation License for the TEMAC IP.
Board Support Files
- Nexys Video Support Files
- These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.
- Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado.
Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server.
General Design Flow
- Open Vivado and select Nexys Video board
- Create an new Vivado Project
- Create empty block design workspace inside the new project
- Add required IP blocks using the IP integrator tool and build Hardware Design
- Validate and save block design
- Create HDL system wrapper
- Run design Synthesis and Implementation
- Generate Bit File
- Export Hardware Design including the generated bit stream file to SDK tool
- Launch SDK
Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.
- Create new application project and select default Hello World template
- Program FPGA
- Run configuration by selecting the correct UART COM Port and Baud Rate
1. Creating a New Project
1.4) If you have followed the Board Support File Wiki guide then click Next and select Boards. From the filter options make required selections for Vendor, Display Name and Board Revision. Nexys Video should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.
At this point you have successfully created a project that will properly communicate with the Nexys Video.
2. Creating the Block Design
2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.
For our design, we will use the IP Integrator to create a new block design.
Add the Microblaze Core:
2.3) An empty design workspace is created where you can add IP blocks. You can click on the “Add IP” message prompt on the top or click on the Add IP button. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for “Microblaze” and double click on it to add the IP block to your empty design.
Adding the Necessary Output Clocks:
Adding More Interrupts:
3. Adding the IP Cores
3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:- Memory Interface Generator - AXI Uartlite - AXI Ethernet Subsystem - AXI Timer
4. Configuring and Routing the IP Cores
4.1) Click Run Block Automation and run it for the mig_7series_0 block.
When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys Video. Click OK to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals.
Routing the Missing Connections
4.6) The Concat block takes interrupt inputs and sends them to the Microblaze controller.
Route the following connections to the inputs of the Concat block; order does not matter:
- interrupt on the AXI Timer block.
- mm2s_introut and s2mm_introut on the axi_ethernet_0_dma block.
- mac_irq and interrupt on the axi_ethernet_0 block.
4.11) Click the Validate Design button to make sure that you did not make any errors.
5. Exporting Hardware Design to SDK
6. Launching SDK
7. Inside SDK for Vivado
7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in the system.hdf file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.
Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.
Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.
8. Creating New Application Project in SDK
8.1) Go to File in the main tool bar and select New→Application Project. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the Target Hardware is the correct hardware design. In our case, it will be design_1_wrapper_hw_platform_0.
If for example, you also have another hardware design in the Project Explorer window, then you will also see this design name in the Target Hardware drop down selection list.
Since we only have one hardware design design_1_wrapper_hw_platform_0 this will be our target hardware. Select Create New under Board Support Package. The tool will automatically populate the Board Support Package name to match with the give project name. Click Next.
After completing the previous step, you will see two new folders in the Project Explorer panel. echo_server which contains all the binaries, .C and .H (Header) files, and echo_server_bsp which is the board support folder.
echo_server is our main working source folder. This also contains an important file shown here in the src folder called lscript.ld. This is a Xilinx auto generated linker script file. Double click on this file to open.
9. Verify Linker Script File for Memory Region Mapping
9.1) In the linker script, take a look at the Section to Memory Region Mapping box. If you did the Make DDR3 External step then the target memory region must read mig_7series_0.
10. Setting PHY Link Speed
10.2) Once in Board Support Package Settings select Overview → standalone → lwip141. The configuration table for the lwip141 library should now be visible on the right. Navigate to temac_adapter_options → phy_link_speed. Here you will need to change CONFIG_LINKSPEED_AUTODETECT to CONFIG_LINKSPEED100 so that it looks like the picture below.
11. Programming FPGA with Bit File
11.1) Make sure that the board is turned on and connected to the host PC with the provided micro USB cable. On the main toolbar, click Xilinx Tools → Program FPGA
Make sure that the Hardware Platform is selected as design_1_wrapper_hw_platform_0.
In the software configuration box, under ELF File to Initialize in Block RAM column, the row option must read bootloop. If not, click on the row and select bootloop.
Now click on Program.
12. Setting up the SDK Serial Console and Running the Server
13. Running the Server
14. Testing the Server with Tera Term
14.1) Connect your PC to your board using an Ethernet cable. If using a router, watch the UART console to find out the IP of the Nexys Video echo server, and connect to that IP address. Setting up the connection as static is unnecessary.
14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
14.2.5) Click the Use the following IP address: bullet and type in an IP address “192.168.1.XX”, where XX is a value between 2 and 255, but not 10. This IP must not be the same as another already on your network. Make sure to click within the Subnet mask field to get the 255.255.255.0 mask to autofill. Click Ok and you will have a static IP address.