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vivado:getting_started:start [2018/05/29 20:41] – [10. Finished!] Arthur Brown | vivado:getting_started:start [2023/04/27 17:11] (current) – [10. Finished!] James Colvin | ||
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====== Getting Started with Vivado ====== | ====== Getting Started with Vivado ====== | ||
- | ----- | + | <WRAP center round important 60%> |
- | + | For the most up to date version of this guide, please visit [[programmable-logic/ | |
- | ===== Prerequisites ===== | + | </ |
- | Prior to starting | + | |
- | + | ||
- | Make sure to install [[reference: | + | |
===== Introduction ===== | ===== Introduction ===== | ||
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The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED. | The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED. | ||
- | This guide was created using Vivado 2016.4. | + | **Note:** //While this guide was created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through Vivado 2019.2, the latest version as of time of writing.// |
- | ==== 1. Starting | + | |
+ | ---- | ||
+ | ===== Prerequisites ===== | ||
+ | Prior to starting this guide make sure to install Vivado: | ||
+ | * For versions 2019.2 and later, see [[vivado: | ||
+ | * For versions prior to 2019.2, see [[vivado: | ||
+ | |||
+ | ---- | ||
+ | ===== Guide ===== | ||
+ | ==== 1. Launching | ||
<WRAP group> | <WRAP group> | ||
<WRAP column half> | <WRAP column half> | ||
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== 4. Open Hardware Manager == | == 4. Open Hardware Manager == | ||
- | This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user this is the button to use. | + | This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user, then this is the button to use. |
==== 3. Creating a New Project ==== | ==== 3. Creating a New Project ==== | ||
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* Tools for creating Block Designs | * Tools for creating Block Designs | ||
* // | * // | ||
- | * Allows a developer to verify the output of their deisgn | + | * Allows a developer to verify the output of their design |
* //RTL Analysis// | * //RTL Analysis// | ||
* lets the developer see how the tools are interpreting their code | * lets the developer see how the tools are interpreting their code | ||
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==== 6. Adding a Constraint File ==== | ==== 6. Adding a Constraint File ==== | ||
- | In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download | + | In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download [[https:// |
<WRAP group> | <WRAP group> | ||
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<WRAP column half> | <WRAP column half> | ||
=== 6.4 === | === 6.4 === | ||
- | Make sure that the selected XDC file has been added into the list of sources, then click //Finish//. | + | Make sure that the selected XDC file has been added into the list of sources, and that the //Copy constraint files into project// is checked, then click //Finish//. |
+ | |||
+ | **Note:** //Leaving the Copy... box unchecked means that any editing done to the constraint file will be reflected in the original copy. Checking the box is highly recommended// | ||
</ | </ | ||
<WRAP column half> | <WRAP column half> | ||
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There are five fields to define for each of the module' | There are five fields to define for each of the module' | ||
- | * //Port Name// | + | * **Port Name:** This field defines the name of the port and needs to match one of the names you used in your XDC file. |
- | | + | * **Direction:** This drop-down menu can be set to //input//, //output//, or //inout//, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling. |
- | * //Direction// | + | * **Bus:** This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus. |
- | | + | * **MSB:** The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. |
- | * //Bus// | + | * **LSB:** The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports. |
- | | + | |
- | * //MSB// | + | |
- | | + | |
- | * //LSB// | + | |
- | | + | |
<WRAP round center tip> | <WRAP round center tip> | ||
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<WRAP group> | <WRAP group> | ||
<WRAP column half> | <WRAP column half> | ||
- | The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields.\ | + | The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields. |
Click //Next// to continue. | Click //Next// to continue. | ||
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You should now see one of the LEDs on your board blinking! | You should now see one of the LEDs on your board blinking! | ||
- | Be sure to visit your board' | + | Be sure to visit your board' |
- | {{tag> | + | {{tag> |