Getting Started with Vivado

For the most up to date version of this guide, please visit Getting Started with Vivado for Hardware-Only Designs.


The Vivado Start Page

The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED.

Note: While this guide was created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through Vivado 2019.2, the latest version as of time of writing.


Prior to starting this guide make sure to install Vivado:


1. Launching Vivado

Open the start menu or desktop shortcut created during the installation process.

Open a terminal, cd into a working directory that can be cluttered with temporary Vivado files and logs, then run the following:

source <install_path>/Vivado/<version>/ && vivado

2. The Start Page

This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide.

1. Create New Project

This button will open the New Project wizard. This wizard steps the user through creating a new project. The wizard is stepped through in section 3.

2. Open Project

This button will open a file browser. Navigate to the desired Xilinx Project (.xpr) file and click Open to open the project in Vivado.

3. Open Example Project

This will guide the user through creating a new project based on an example project. These projects will not work on all devices.

4. Open Hardware Manager

This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user, then this is the button to use.

3. Creating a New Project


From the start page, select the Create New Project button to start the New Project Wizard.


The text in this dialog describes the steps that will be taken to create a project. Click Next to continue to the first step.


The first step is to set the name of the project. Vivado will use this name when generating its folder structure.


Do NOT use spaces in your project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click Next to continue.


Now that the project has a name and a place to save its files we need to select the type of project we will be creating. Select RTL Project and make sure to check Do not specify sources at this time. Source files will be added and created after the project has been created. Advanced users may use the other options on this screen, but they will not be covered in this guide.

Click Next to continue.



If your board does not appear in this list, then Digilent's board files haven't yet been installed. If this is the case, revisit the prerequisites section of this guide, then close Vivado and start again from the beginning.

Now it is time to choose the target device. Click the Boards tab at the top of the dialog, then select your board from the list.

Click Next to continue.


The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click Finish.

4. The Flow Navigator

The Flow Navigator is the most important pane of the main Vivado window to know. It is how a user navigates between different Vivado tools.

The Navigator is broken into seven sections:

  • Project Manager
    • Allows for quick access to project settings, adding sources, language templates, and the IP catalog
  • IP Integrator
    • Tools for creating Block Designs
  • Simulation
    • Allows a developer to verify the output of their design prior to programming their device
  • RTL Analysis
    • lets the developer see how the tools are interpreting their code
  • Synthesis
    • Gives access to Synthesis settings and post-synthesis reports
  • Implementation
    • Gives access to Implementation settings and post-implementation reports
  • Program and Debug
    • Access to settings for bitstream generation and the Hardware Manager

5. The Project Manager

This tool is where most development will occur and is the initial tool open after creating a new project.

The Project Manager consists of four panes, Sources, Properties, Results, and the Workspace.

The Sources pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the Design Sources folder, constraints are kept under the Constraints folder, and simulation files are kept under the Simulation Sources folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting Add Sources or by clicking the Add Sources button ().

The Properties pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.

The unnamed pane at the bottom of the Project Manager window consists of several different useful tools for debugging a project. The most important one to know is the Messages tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.

These tools can be accessed by selecting the different tabs at the bottom of this pane.

The Tcl Console is a tool that allows for running commands directly without the use of the main user interface. Some messages may link to the Tcl Console to provide more information regarding an error.

The Reports tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.

The Log displays the output from the latest Synthesis, Implementation, and Simulation runs. Digging into this is usually not necessary as the reports and messages view store the information in the log in a more readable format.

The last tool is the Design Runs. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.

The most important pane in the Project Manager is the Workspace. The Workspace is where reports are opened for viewing and HDL/constraints files are opened for editing. Initially the Workspace displays the Project Summary which show some basic information from some of the reports.

6. Adding a Constraint File

In order to connect HDL code with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent has produced a Xilinx Design Constraint (XDC) file for each of our boards. Download, the ZIP Archive containing each of these master XDC files, then extract it in a location you will remember.


In the Project Manager section of the Flow Navigator, click the button. In the wizard that pops up, select Add or create constraints then click Next.


At this stage, Vivado provides a list of all of the constraint files that will be added or created when we click Finish. Currently this list is empty, this will change when files have been added or created. A constraint file will not be created from scratch in this guide, so click Add Files.


Find the directory you extracted the archive into, then click on the file for your board. This should add the name of the file to the File Name field.

Click OK to continue.


Make sure that the selected XDC file has been added into the list of sources, and that the Copy constraint files into project is checked, then click Finish.

Note: Leaving the Copy… box unchecked means that any editing done to the constraint file will be reflected in the original copy. Checking the box is highly recommended


In the Sources pane of the Project Manager, expand the Constraints folder, then double click on the XDC file you just added. Each of Digilent's XDC files contains constraints for each of the commonly used peripherals on their respective boards. For this demo, constraining the default system clock and a single led is required.

Find and uncomment the lines that call get_ports on the names led[0] and clk by removing the '#' symbol at the beginning of the line. On some boards the clock port will consist of two different ports, clk_p and clk_n. The clock port is occasionally named something like sysclk, but should appear at the top of the XDC file. Uncomment the create_clock line that follows the clock port/s definition as well.


A board using clk_p/clk_n pins means that the input clock that uses differential logic. If you want to know more read this article on low-voltage differential signalling.

Change the name inside of the get_ports call to 'led' from 'led[0]'. Do the same for the clock if it is something other than 'clk' or 'clk_p' and 'clk_n'.

7. Creating a Verilog Source File


In the Project Manager section of the Flow Navigator, click the button again. Select Add or create design sources then click Next.


As before, at this stage, we will be provided a list of all of the source files that will be added or created when we click Finish. Instead of clicking Add Files, click Create File.


It is also possible to add existing source files in the same way as we added the constraint file above.


You will be prompted to select a File type, File name, and File location. Make sure to pick Verilog and <Local to project> for the type and location. Give your file a name ending in '.v'.


Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click OK to continue.


Make sure that the new Verilog source file has been added into the list of sources, then click Finish.


Unlike when the constraint file was added, at this point a Define Module dialog will pop up. You can rename your Verilog module using the Module name field, but this is unnecessary. The Verilog module's clock and led ports need to be defined. Clicking the Add () button will add an empty slot for a port to the I/O Port Definitions list.

There are five fields to define for each of the module's I/O ports:

  • Port Name: This field defines the name of the port and needs to match one of the names you used in your XDC file.
  • Direction: This drop-down menu can be set to input, output, or inout, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling.
  • Bus: This can be checked or not, when checked, this port consists of multiple single bit signals, grouped into a single bus.
  • MSB: The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.
  • LSB: The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.


If you are defining a module which will be instantiated in another module, which we will not go into in this guide, be aware that the port names should not be declared in the XDC, this is only done for your 'top' module.

If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock ports that were uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock port that was uncommented in your XDC file.

Add a single-bit output port with the same name as the LED port that was uncommented in your XDC file.

Once these two or three ports have been added, click OK to continue.


At this point, the new source file will be added to the Design Sources folder in the Sources pane of the Project Manager. Expand this folder and double click on the file to open it.

Next, some Verilog code needs to be written to define how the design will actually behave.

Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following code:

reg [24:0] count = 0;
assign led = count[24];
always @ (posedge(clk)) count <= count + 1;

If your board is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line:

wire clk;
IBUFGDS clk_inst (

It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. The system clock period in nanoseconds can be found on the create_clock line of the XDC file.

After completing this guide, it is suggested to try changing the provided Verilog code so that the clock blinks at 1 Hertz - changing the XDC file beyond commenting or uncommenting entire lines is not recommended.

8. Synthesis, Implementation, and Bitstream Generation

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

This starts with Synthesis. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.

Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.

The Bitstream Generator generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.

9. The Hardware Manager

The Hardware Manager is used for programming the target device.

The first step to programming a device is to connect the Vivado Hardware Server to it. There are two ways to do this.

1. Open New Hardware Target

The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the Open Hardware Target wizard either open the Hardware Manager and click the link in the green banner or click the button in the Flow Navigator under . From the drop-down that opens, select .

Once the wizard opens, click Next.

The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the Host Name and Port fields.

Click Next to continue.

This screen gives a list of devices connected to the hardware server. If there is only one connected it should be the only device shown. If there are multiple connected devices, determine the serial number of the device to connect to and find it in the list.

Click Next to continue.

The final screen shows a summary of the options selected in the wizard. Verify the information and click Finish. The board is now connected to the hardware manager.

2. Auto-Connect

The second method is to automatically open the target. To get to the button either open the Hardware Manager and click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens select . Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.


To program the device with the bit file generated earlier, either click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens, select the device to program (Example: ) and the following window will open:

The Bitstream File field should be automatically filled in with the bit file generated earlier. If not, click the button at the right end of the field and navigate to
<Project Directory>/<Project Name>.runs/impl_1/ and select the bit file (Example: ). Now click Program. This will connect to the board, clear the current configuration, and program using the new bit file.

10. Finished!

You should now see one of the LEDs on your board blinking!

Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found here.