Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
programmable-logic:cora-z7:reference-manual [2023/02/06 17:11] – Arthur Brownprogrammable-logic:cora-z7:reference-manual [2023/06/22 21:14] (current) – Arthur Brown
Line 18: Line 18:
 ---- ----
  
-====== Features ======+===== Features =====
  
   * **ZYNQ Processor**   * **ZYNQ Processor**
Line 32: Line 32:
     * Programmable from JTAG and microSD card     * Programmable from JTAG and microSD card
   * **Memory**   * **Memory**
-    * 512MB DDR3 with 16-bit bus @ 1050Mbps+    * 512MB DDR3 with 16-bit bus @ 525 MHz (1050 MT/s)
     * microSD slot     * microSD slot
   * **Power**   * **Power**
Line 70: Line 70:
 | 10       | User push buttons                         |          |                                         | | 10       | User push buttons                         |          |                                         |
  
-====== Purchasing Options and Board Variants ======+===== Purchasing Options and Board Variants =====
  
 A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
Line 93: Line 93:
  
 ---- ----
-====== Software Support ======+===== Software Support =====
  
 The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.
Line 104: Line 104:
  
 ---- ----
-====== Functional Description ======+===== Functional Description =====
  
 ===== 1 Power Supplies ===== ===== 1 Power Supplies =====
Line 258: Line 258:
 ===== 4 DDR3L Memory ===== ===== 4 DDR3L Memory =====
  
-The Cora Z7 includes a Micron MT41K256M16HA-125 DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation. +The Cora Z7 includes a single DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.  
 + 
 +**Note:** //The Cora Z7 may use any of the Micron MT41K256M16HA-125, Micron MT41K256M16TW-107, Zentel A3T4GF40ABF-GML, or Zentel A3T4GF40BBF-HP DDR3 parts. User projects targeting previous revisions of the board which only included the MT41K256M16HA-125 part will be backward-compatible with any of the loaded parts.//
  
 The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported.  The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. 
Line 359: Line 361:
 ===== 9 Clock Sources ===== ===== 9 Clock Sources =====
  
-The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[:vivado:installing-vivado:start#installing_digilent_board_files|Installation Instructions]]) can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.+The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 MT/s). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[:vivado:installing-vivado:start#installing_digilent_board_files|Installation Instructions]]) can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.
  
 The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor.  The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor. 
Line 506: Line 508:
  
 ---- ----
-====== Hardware errata ======+===== Hardware errata =====
 Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^