Cora Z7 Reference Manual
The Cora Z7-10 variant is now retired in our store. The Cora Z7-07S is not affected and will remain in production.
The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of software defined peripherals and controllers, tailored for the target application.
The Cora Z7’s wide array of hardware interfaces, from a 1Gbps Ethernet PHY to analog-to-digital converters and general-purpose input/output pins, make it an ideal platform for the development of a vast variety of embedded applications. The small form factor and mounting holes make the Cora Z7 ready to be used as one component of a larger solution. The on-board SD Card slot, Ethernet, and Power solution allow the Cora Z7 to operate independently of a host computer.
- ZYNQ Processor
- 667MHz single-core (*dual-core) Cortex-A9 processor
- FPGA Programmable logic equivalent to Artix-7 FPGA
- 3,600 Programmable logic slices (*4,400)
- 60 DSP slices (*80)
- 225 KB of block RAM (*270 KB)
- DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
- High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
- Low-bandwidth peripheral controllers: SPI, UART, CAN, I2C
- Dual-channel, 1 MSPS internal analog-digital converter
- Programmable from JTAG and microSD card
- 512MB DDR3 with 16-bit bus @ 1050Mbps
- microSD slot
- Powered from USB or any 4.5V-5.5V external power source
- USB and Ethernet
- Gigabit Ethernet PHY with 48-bit globally unique EUI-48/64™ compatible identifier available on sticker
- USB-JTAG programming circuitry
- USB-UART bridge
- USB OTG PHY (supports host only)
- Push-buttons and LEDs
- Two Push-buttons
- Two RGB LEDs
- Expansion Connectors
- Two Pmod connectors
- 16 Total FPGA I/O
- Arduino/chipKIT Shield connector
- Up to 49 Total FPGA Digital I/O
- 6 Single-ended 0-3.3V Analog inputs to XADC
- 8 Differential 0-1.0V Analog inputs to XADC
- Unloaded expansion header
- 12 additional FPGA Digital I/O
(*Z7-10 variant in parentheses where different)
|1||Power select jumper (Ext. supply / USB)||11||microSD card slot (underside of board)|
|2||Power jack (for optional ext. supply)||12||USB host port|
|3||Shared USB JTAG / UART port||13||FPGA programming DONE LED|
|4||Unloaded expansion header||14||Processor subsystem reset button|
|5||Pmod connectors||15||Ethernet port|
|6||SPI header (Arduino/ChipKIT compatible)||16||Power on reset button|
|7||Arduino/ChipKIT shield connectors||17||Power good LED|
|8||Programming mode jumper (JTAG / microSD)||18||Zynq-7000|
|9||User tri-color LEDs||19||DDR3L memory|
|10||User push buttons|
Purchasing Options and Board Variants
A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the “Cora Z7”. When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below:
|Product Variant||Cora Z7-07S||Cora Z7-10 (No longer in production)|
|ARM Processor Cores||1||2|
|1 MSPS On-chip ADC||Yes||Yes|
|Look-up Tables (LUTs)||14,400||17,600|
|Block RAM||225 KB||270 KB|
|Clock Management Tiles||2||2|
For more information on purchasing, see the Cora Z7 Product Page.
The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.
Master XDC files and Board files for the Cora Z7-10 and Z7-07S are available through the Cora Z7 Resource Center. These files are used to inform Vivado about how the Zynq chip on the Cora is configured and connected to the rest of the Cora.
Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the Cora Z7 Resource Center.
1 Power Supplies
The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header.
A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or Digilent Support for further help.
Figure 1.1 Cora Z7 Power Circuit
The USB port can deliver enough power for the vast majority of designs. However, a few demanding applications, including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply can be used by plugging into the Power Jack (J15). The supply must use a coaxial, center-positive 2.1mm (or 2.5mm) internal-diameter plug, and provide a DC voltage of 5 Volts. The supply should provide a minimum current of 1 amp. Ideally, the supply should be capable of providing 20 Watts of power (5 Volts DC, 4 amps). If the USB port is to be used to deliver power, the Power Select Jumper (JP3) should be set to “USB”. If an external power supply is to be used, JP3 should be set to “EXT” instead.
Voltage regulator circuits from Dialog Semiconductor and ON Semiconductor create the required 3.3V, 1.8V, 1.35V, and 1.00V supplies from the 5V power source. In the event that an external supply or battery pack is used, the on-board Monolithic Power Systems 5V regulator (IC12) provides the 5V source. Table 1.1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs). The 0.675V supply is created by a simple Voltage divider circuit consisting of two 10 KOhm resistors, sourced from the 1.35V rail.
|5.0V||Onboard Regulators, Arduino/chipKit Shield Connector, RGB LEDs||IC4: ON Semiconductor NCP3801)|
|3.3V||FPGA I/O, USB port, Ethernet||IC15: Dialog Semiconductor DA9062||2A|
|1.0V||FPGA, Ethernet||IC15: Dialog Semiconductor DA9062||2.5A|
|1.8V||FPGA Auxiliary, USB port, Ethernet||IC15: Dialog Semiconductor DA9062||1.5A|
|1.35V||FPGA, DDR3L memory||IC15: Dialog Semiconductor DA9062||2.5A|
|1.8V||FPGA XADC||IC15: Dialog Semiconductor DA9062||100mA|
Table 1.1. Cora Z7 Power Rails.
2 Zynq APSoC Architecture
The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic (PL). Figure 2.1 shows an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010 or Zynq-7007S devices.
Figure 2.1 Zynq APSoC architecture
The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.
There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the Zynq Technical Reference Manual.
Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the Cora Z7 Resource Center can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals.
|MIO 500 (3.3 V)||Peripherals|
|Pin||Configuration Mode||ENET 0||USB 0||Shield||UART 0|
|11||USB Over Current|
|MIO 501 (1.8V)||Peripherals|
|Pin||ETH 0||USB 0||SDIO 0|
Table 2.1. MIO Pinout
3 Zynq Configuration
Unlike Xilinx FPGA devices, APSoC devices such as the Zynq-7007S are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application. The boot process is broken into three stages:
After the Cora Z7 is powered on, or the Zynq is reset (in software or by pressing SRST), the processor (CPU0 for the Cora Z7-10) begins executing an internal piece of read-only code called the BootROM. If and only if the Zynq was just powered on, the BootROM will first latch the state of the mode pins into the mode register (the mode pins are attached to JP2 on the Cora Z7). If the BootROM is being executed due to a reset event, then the mode pins are not latched, and the previous state of the mode register is used. This means that the Cora Z7 needs a power cycle to register any change in the programming mode jumper (JP2). Next, the BootROM copies an FSBL from the form of non-volatile memory specified by the mode register to the 256 KB of internal RAM within the APU (called On-Chip Memory, or OCM). The FSBL must be wrapped up in a Zynq Boot Image in order for the BootROM to properly copy it. The last thing the BootROM does is hand off execution to the FSBL in OCM.
During this stage, the FSBL first finishes configuring the PS components, such as the DDR memory controller. Then, if a bitstream is present in the Zynq Boot Image, it is read and used to configure the PL. Finally, the user application is loaded into memory from the Zynq Boot Image, and execution is handed off to it.
The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the Zynq Technical Reference manual.
The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools.
The Cora Z7 supports two different boot modes: microSD and JTAG. The boot mode is selected using the Mode jumper (JP2), which affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the Cora Z7.
Figure 3.1. Cora Z7 configuration pins.
The two boot modes are described in the following sections.
3.1 microSD Boot Mode
The Cora Z7 supports booting from a microSD card inserted into connector J10. The following procedure will allow the Zynq to boot from microSD with a standard Zynq Boot Image created with the Xilinx tools:
- Format the microSD card with a FAT32 file system.
- Copy the Zynq Boot Image created with Xilinx SDK to the microSD card.
- Rename the Zynq Boot Image on the microSD card to BOOT.bin.
- Eject the microSD card from the host computer and insert it into connector J10 on the Cora Z7.
- Attach a power source to the Cora Z7 and select it using JP3.
- Place a jumper on JP2, shorting the two pins together.
- Turn the board on. The board will now boot the image on the microSD card.
3.2 JTAG Boot Mode
When placed in JTAG boot mode, the processor will wait until software is loaded by a host computer using the Xilinx tools. After software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK.
It is also possible to directly configure the PL over JTAG, independent of the processor. This can be done using the Vivado Hardware Server.
4 DDR3L Memory
The Cora Z7 includes a Micron MT41K256M16HA-125 DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported.
The Cora Z7 was routed with 40 ohm (+/-10%) trace impedance for single-ended signals, and differential clock and strobes set to 80 ohms (+/-10%). A feature called DCI (Digitally Controlled Impedance) is used to match the drive strength and termination impedance of the PS pins to the trace impedance. On the memory side, the DDR3L chip calibrates its on-die termination and drive strength using a 240 ohm resistor on the ZQ pin.
Due to layout reasons, the two data byte groups (DQ[0-7], DQ[8-15]) were swapped. To the same effect, the data bits inside byte groups were swapped as well. These changes are transparent to the user. During the whole design process the Xilinx PCB guidelines were followed.
Both the memory chip and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of 0.675V is created with a simple resistor divider and is available to the Zynq as external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings range from the actual memory flavor to the board trace delays. For your convenience, the Cora Z7 Vivado board files are available on the Cora Z7 Resource Center and automatically configure the Zynq Processing System IP core with the correct parameters.
For best DDR3L performance, DRAM training is enabled for write leveling, read gate, and read data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays, process variations and thermal drift. Optimum starting values for the training process are the board delays (propagation delays) for certain memory signals.
Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design.
For more details on memory controller operation, refer to the Xilinx Zynq Technical Reference manual.
5 USB UART Bridge (Serial Port)
The Cora Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J12) that lets you use PC applications to communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.
The Zynq presets file (available through the Cora Z7 Resource Center) takes care of mapping the correct MIO pins to the UART 0 controller and uses the following default protocol parameters: 115200 baud rate, 1 stop bit, no parity, 8-bit character length.
Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD5) and the receive LED (LD4). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.
The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features into a single device allows the Cora Z7 to be programmed, communicated with via UART, and powered from a computer attached with a single Micro USB cable.
The DTR signal from the UART controller on the FT2232HQ is connected to MIO12 of the Zynq device via JP1. Should the Arduino IDE be ported to work with the Cora Z7, this jumper can be shorted and MIO12 could be used to place the Cora Z7 in a “ready to receive a new sketch” state. This would mimic the behavior of typical Arduino IDE boot-loaders.
6 microSD Slot
The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the Zynq Technical Reference manual, SDIO host mode is the only mode supported.
|Signal Name||Description||Zynq Pin||SD Slot Pin|
Table 6.1. microSD pinout
The SD slot is powered from the 3.3V rail, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter is used to perform the necessary translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen in Figure 6.1. Mapping out the correct pins and configuring the interface is handled by the Cora Z7 Zynq presets file, available through the Cora Z7 Resource Center.
Figure 6.1. microSD slot signals
Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended.
Refer to section 3.1, microSD Boot Mode, for information on how to boot the Cora Z7 from an SD card. For more information, consult the Zynq Technical Reference manual.
7 USB Host
The Cora Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The USB0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.
The Cora Z7 is technically an “embedded host”, because it does not provide the required 150 µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Cora Z7 so that it complies with the general purpose USB host requirements by loading C35 with a 150 µF capacitor. Only those experienced at soldering small components on PCBs should attempt this rework. Many USB peripheral devices will work just fine without loading C35. Whether the Cora Z7 is configured as an embedded host or a general purpose host, it can provide 1A on the 5V VBUS line.
Note that if your design uses the USB Host port (embedded or general purpose), then the Cora Z7 should be powered via a wall adapter capable of providing more power.
8 Ethernet PHY
The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively.
Figure 8.1. Ethernet PHY signals
After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured.
Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD9) and valid link state (LD8). Table 8.1 shows the default behavior.
|LINK||LD8||Steady On||Link 10/100/1000|
|Blinking 0.4s ON, 2s OFF||Link, Energy Efficient Ethernet (EEE) mode|
|ACT||LD9||Blinking||Transmitting or Receiving|
Table 8.1. Ethernet status LEDs.
The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Cora Z7 Zynq Presets file, available on the Cora Z7 Resource Center.
Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.
The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer.
The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source.
On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/64™ compatible identifier.
For more information on using the Gigabit Ethernet MAC, refer to the Zynq Technical Reference manual.
9 Clock Sources
The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package (Installation Instructions) can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.
The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor.
The PL of the Zynq also includes Mixed-Mode Clock Managers (MMCM) and PLLs that can be used to generate clocks with precise frequencies and phase relationships. Any of the four PS reference clocks or the 125 MHz external reference clock can be used as an input to the MMCMs and PLLs. Both the Cora Z7-07S and Z7-10 include 2 MMCM's and 2 PLL's. For a full description of the capabilities of the Zynq PL clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx.
Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low.
Figure 9.1. Cora Z7 Clocking
10 Reset Sources
10.1 Power-on Reset Signals
The Zynq Processing System (PS) supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Cora Z7 drives this signal from the nRESET signal of the DA9062 DC-DC converter system in order to hold the system in reset until all power supplies are valid. A push-button, labeled RESET, can be used to toggle the power-on reset signal.
Note: The power-on reset will not reset attached shields.
10.2 Processor Subsystem Reset
The external system reset, labeled SRST, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the OCM. The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled.
The SRST button also causes the CK_RST signal to toggle and trigger a reset on any attached shields.
11 Basic I/O
The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are “momentary” switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
Figure 11.1. Cora Z7 Basic I/O
11.1 Tri-Color LEDs
The Cora Z7 board contains two tri-color LEDs. Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the signal corresponding to one of these colors high will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding signals need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color.
Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-color LEDs. Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an uncomfortably bright level. This can be avoided by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color led. Individually adjusting the duty cycle of each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.
12 Pmod Connectors
Pmod connectors are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 15.1. The VCC and Ground pins can deliver up to 100mA of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail current limits listed in the “Power Supplies” section).
Warning: Since the Pmod pins are connected to Zynq PL I/O pins using a 3.3V logic standard, care should be taken not to drive these pins over 3.4V.
Figure 12.1. Pmod Port Diagram
Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information.
Each Pmod connector found on Digilent FPGA boards falls into one of four categories: standard, MIO connected, XADC, or high-speed. The Cora Z7 has two Pmod connectors, both of which are of the high-speed type. The following section describes the high-speed type of Pmod connector.
12.1 High-Speed Pmods
The High-speed Pmods have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Cora Z7 ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds. The signals are paired to the adjacent signals in the same row: pins 1 and 2, pins 3 and 4, pins 7 and 8, and pins 9 and 10.
Traces are routed 100 ohm (+/- 10%) differential.
If pins on this port are used as single-ended signals, coupled pairs may exhibit crosstalk. In applications where this is a concern, one of the signals should be grounded (drive it low from the FPGA) and use its pair for the signal-ended signal.
Since the High-Speed Pmods have 0-ohm shunts instead of protection resistors, the operator must take care to prevent any shorts.
13 Arduino/chipKIT Shield Connector
The Cora Z7 can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Cora S7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 45 pins connected to the FPGA for general purpose Digital I/O. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another six (labeled AN6-11) can be used as differential analog input pairs with an input range of 0V-1.0V.
Note: The Cora Z7 is not compatible with shields that output 5V digital or analog signals. Driving pins on the Cora Z7 shield connector above 3.4V may cause damage to the FPGA.
Figure 13.1 diagrams the pins found on the shield connector of the Cora Z7.
Figure 13.1. Shield connector pin diagram.
|Pin Name||Shield Function||Cora Z7 Connection|
|IO0-IO13, IO26-IO41, A (IO42)||General purpose I/O pins||See Section titled “Shield Digital I/O”|
|SCL||I2C Clock||See Section titled “Shield Digital I/O”|
|SDA||I2C Data||See Section titled “Shield Digital I/O”|
|SCK||SPI Clock||See Section titled “Shield Digital I/O”|
|SS||SPI Slave Select||See Section titled “Shield Digital I/O”|
|MOSI||SPI Master-Out Slave-In||See Section titled “Shield Digital I/O”|
|MISO||SPI Master-In Slave-In||See Section titled “Shield Digital I/O”|
|A0-A5||Single-Ended Analog Input||See Section titled “Shield Analog I/O”|
|A6-A11||Differential Analog Input||See Section titled “Shield Analog I/O”|
|V_P, V_N||Dedicated Differential Analog Input||See Section titled “Shield Analog I/O”|
|XGND||XADC Analog Ground||Connected to net used to drive the XADC ground reference on the FPGA (VREFN)|
|N/C||Not Connected||Not Connected|
|IOREF||Digital I/O Voltage reference||Connected to the Cora Z7 3.3V Power Rail (See the “Power Supplies” section)|
|RST||Reset to Shield||Connected to the red “SRST” button and a Digital I/O of the FPGA. When JP1 is shorted, it is also connected to the DTR signal of the FTDI USB-UART bridge.|
|3V3||3.3V Power Rail||Connected to the Cora Z7 3.3V Power Rail (See the “Power Supplies” section)|
|5V0||5.0V Power Rail||Connected to the Cora Z7 5.0V Power Rail (See the “Power Supplies” section)|
|GND, G||Ground||Connected to the Ground plane of Cora Z7|
Table 13.1. Cora Z7 Shield Pinout
13.1 Shield Digital I/O
The pins connected directly to the FPGA can be used as general purpose inputs or outputs. These pins include the I2C, SPI, and general purpose I/O pins. There are 200 Ohm series resistors between the FPGA and the digital I/O pins to help provide protection against accidental short circuits. The absolute maximum and recommended operating voltages for these pins are outlined in Table 13.1.1.
|Absolute Minimum Voltage||Recommended Minimum Operating Voltage||Recommended Maximum Operating Voltage||Absolute Maximum Voltage|
|Powered||-0.4 V||-0.2 V||3.4 V||3.75 V|
|Unpowered||-0.4 V||N/A||N/A||0.55 V|
Table 13.1.1. Shield Voltage Specifications
For more information on the electrical characteristics of the pins connected to the FPGA, please see the Zynq-7000 datasheet from Xilinx.
The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind.
13.2 Shield Analog I/O
The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Cora Z7's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as digital inputs or outputs, as they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 13.2.1).
Figure 13.2.1. Single-Ended Analog Inputs
The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 13.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even-numbered pins are connected to the positive pins of the trio and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O.
Figure 13.2.2. Differential Analog Inputs
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 13.2.3 for this pair of pins is loaded on the Cora Z7.
Figure 13.2.3. Dedicated Analog Input Pair
The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via either the Dynamic Reconfiguration Port (DRP) or an AXI interface connected to the Zynq PS. These interfaces also provide access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter”. A demo that uses the XADC core is available through the Cora Z7 Resource Center.
14 Unloaded Expansion Header
The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can be found in the Cora Z7 master XDC file, available through the Cora Z7 Resource Center.
Figure 14.1. Unloaded Expansion Header
Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
|Cora Z7||All||All|| Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:|
[PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
The negative values are due to CK trace being shorter than any of the four DQS traces.
In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process.
Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://support.xilinx.com/s/article/53039. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted.
To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.
|will not fix|