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programmable-logic:cora-z7:reference-manual [2022/03/18 22:01] – z7-07s variant first in feature list Arthur Brown | programmable-logic:cora-z7:reference-manual [2023/06/22 21:14] (current) – Arthur Brown | ||
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====== Cora Z7 Reference Manual ====== | ====== Cora Z7 Reference Manual ====== | ||
- | <WRAP round important> | + | <WRAP round info> |
- | The Cora Z7-10 variant is no longer | + | The Cora Z7-10 variant is now retired |
</ | </ | ||
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---- | ---- | ||
- | ====== Features | + | ===== Features ===== |
* **ZYNQ Processor** | * **ZYNQ Processor** | ||
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* Programmable from JTAG and microSD card | * Programmable from JTAG and microSD card | ||
* **Memory** | * **Memory** | ||
- | * 512MB DDR3 with 16-bit bus @ 1050Mbps | + | * 512MB DDR3 with 16-bit bus @ 525 MHz (1050 MT/s) |
* microSD slot | * microSD slot | ||
* **Power** | * **Power** | ||
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| 10 | User push buttons | | 10 | User push buttons | ||
- | ====== Purchasing Options and Board Variants | + | ===== Purchasing Options and Board Variants ===== |
- | The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. | + | A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. |
The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, | The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, | ||
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- | ====== Software Support | + | ===== Software Support ===== |
The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. | The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. | ||
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Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, | Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, | ||
- | Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https:// | + | /* Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https:// |
---- | ---- | ||
- | ====== Functional Description | + | ===== Functional Description ===== |
===== 1 Power Supplies ===== | ===== 1 Power Supplies ===== | ||
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The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. | The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. | ||
- | A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http:// | + | A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http:// |
{{ reference: | {{ reference: | ||
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The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, | The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, | ||
- | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, | + | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, |
Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. | Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. | ||
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**Stage 2** | **Stage 2** | ||
- | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/ | + | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/ |
The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | ||
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===== 4 DDR3L Memory ===== | ===== 4 DDR3L Memory ===== | ||
- | The Cora Z7 includes a Micron MT41K256M16HA-125 | + | The Cora Z7 includes a single |
+ | |||
+ | **Note:** //The Cora Z7 may use any of the Micron MT41K256M16HA-125, | ||
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. | The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. | ||
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Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. | Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. | ||
- | For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/ | + | For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/ |
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===== 6 microSD Slot ===== | ===== 6 microSD Slot ===== | ||
- | The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/ | + | The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/ |
| **Signal Name** | | **Signal Name** | ||
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Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. | Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. | ||
- | Refer to section 3.1, [[# | + | Refer to section 3.1, [[# |
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On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/ | On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/ | ||
- | For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/ | + | For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/ |
---- | ---- | ||
===== 9 Clock Sources ===== | ===== 9 Clock Sources ===== | ||
- | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: | + | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 MT/s). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: |
The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, | The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, | ||
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//Table 13.1.1. Shield Voltage Specifications// | //Table 13.1.1. Shield Voltage Specifications// | ||
- | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/ | + | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/ |
The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. | The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. | ||
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- | ====== Hardware errata | + | ===== Hardware errata ===== |
Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. | Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. | ||
^ Product Name ^ Variant | ^ Product Name ^ Variant | ||
- | | Cora Z7 | All | All | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado > | + | | Cora Z7 | All | All | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado > |
{{tag>rm doc cora-z7}} | {{tag>rm doc cora-z7}} |