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programmable-logic:cora-z7:reference-manual [2022/03/18 21:46] – [Purchasing Options and Board Variants] add note about -10 eol Arthur Brownprogrammable-logic:cora-z7:reference-manual [2023/06/22 21:14] (current) – Arthur Brown
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 ====== Cora Z7 Reference Manual ====== ====== Cora Z7 Reference Manual ======
 +
 +<WRAP round info>
 +The Cora Z7-10 variant is now retired in our store. The Cora Z7-07S is not affected and will remain in production. 
 +</WRAP>
 +
 The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of software defined peripherals and controllers, tailored for the target application. The Digilent Cora Z7 is a ready-to-use, low-cost, and easily embeddable development platform designed around the powerful Zynq-7000 All-Programmable System-on-Chip (APSoC) from Xilinx. The Zynq-7000 architecture tightly integrates a single or dual core 667MHz ARM Cortex-A9 processor with a Xilinx 7-series FPGA. This pairing grants the ability to surround the processor with a unique set of software defined peripherals and controllers, tailored for the target application.
  
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 ---- ----
  
-====== Features ======+===== Features =====
  
   * **ZYNQ Processor**   * **ZYNQ Processor**
-    * 667MHz dual-core (*single-core) Cortex-A9 processor+    * 667MHz single-core (*dual-core) Cortex-A9 processor
     * FPGA Programmable logic equivalent to Artix-7 FPGA     * FPGA Programmable logic equivalent to Artix-7 FPGA
-      * 4,400 Programmable logic slices (*3,600) +      * 3,600 Programmable logic slices (*4,400) 
-      * 80 DSP slices (*60) +      * 60 DSP slices (*80) 
-      * 270 KB of block RAM (*225 KB)+      * 225 KB of block RAM (*270 KB)
     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
     * High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO     * High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
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     * Programmable from JTAG and microSD card     * Programmable from JTAG and microSD card
   * **Memory**   * **Memory**
-    * 512MB DDR3 with 16-bit bus @ 1050Mbps+    * 512MB DDR3 with 16-bit bus @ 525 MHz (1050 MT/s)
     * microSD slot     * microSD slot
   * **Power**   * **Power**
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       * 12 additional FPGA Digital I/O       * 12 additional FPGA Digital I/O
  
-(*Z7-07S variant in parentheses where different)+(*Z7-10 variant in parentheses where different)
  
 {{ reference:programmable-logic:cora-z7:cora-z7-callout.png?800 |}} {{ reference:programmable-logic:cora-z7:cora-z7-callout.png?800 |}}
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 | 10       | User push buttons                         |          |                                         | | 10       | User push buttons                         |          |                                         |
  
-====== Purchasing Options and Board Variants ======+===== Purchasing Options and Board Variants =====
  
-The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.+A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
  
 The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below: The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below:
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 For more information on purchasing, see the [[https://digilent.com/shop/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/|Cora Z7 Product Page]]. For more information on purchasing, see the [[https://digilent.com/shop/cora-z7-zynq-7000-single-core-and-dual-core-options-for-arm-fpga-soc-development/|Cora Z7 Product Page]].
  
 +/*
 **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[programmable-logic:arty-z7:start|Arty Z7-20]] //if they are interested in these types of applications.// **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[programmable-logic:arty-z7:start|Arty Z7-20]] //if they are interested in these types of applications.//
 +*/
  
 ---- ----
-====== Software Support ======+===== Software Support =====
  
 The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.
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 Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[start|Cora Z7 Resource Center]]. Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, see the [[start|Cora Z7 Resource Center]].
  
-Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilentinc.com|Digilent Forum]].+/* Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilent.com|Digilent Forum]]. */
  
 ---- ----
-====== Functional Description ======+===== Functional Description =====
  
 ===== 1 Power Supplies ===== ===== 1 Power Supplies =====
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 The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header.
  
-A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http://forum.digilentinc.com|Digilent Support]] for further help.+A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http://forum.digilent.com|Digilent Support]] for further help.
  
 {{ reference:programmable-logic:cora-z7:cora-power.png?nolink&600 |Figure 1.1 Cora Z7 Power Circuit}} {{ reference:programmable-logic:cora-z7:cora-power.png?nolink&600 |Figure 1.1 Cora Z7 Power Circuit}}
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 The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]]. 
  
 Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals.  Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. 
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools.
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 ===== 4 DDR3L Memory ===== ===== 4 DDR3L Memory =====
  
-The Cora Z7 includes a Micron MT41K256M16HA-125 DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation. +The Cora Z7 includes a single DDR3L memory component, creating a single rank 16-bit wide interface and a total of 512 MiB (Mebi-byte, or 536,870,912 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.  
 + 
 +**Note:** //The Cora Z7 may use any of the Micron MT41K256M16HA-125, Micron MT41K256M16TW-107, Zentel A3T4GF40ABF-GML, or Zentel A3T4GF40BBF-HP DDR3 parts. User projects targeting previous revisions of the board which only included the MT41K256M16HA-125 part will be backward-compatible with any of the loaded parts.//
  
 The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported.  The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. 
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 ===== 6 microSD Slot ===== ===== 6 microSD Slot =====
  
-The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.+The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
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 Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended.  Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. 
  
-Refer to section 3.1, [[#microsd-boot-mode|microSD Boot Mode]], for information on how to boot the Cora Z7 from an SD card. For more information, consult the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+Refer to section 3.1, [[#microsd-boot-mode|microSD Boot Mode]], for information on how to boot the Cora Z7 from an SD card. For more information, consult the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
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 On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/64™ compatible identifier. On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/64™ compatible identifier.
  
-For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
 ===== 9 Clock Sources ===== ===== 9 Clock Sources =====
  
-The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[:vivado:installing-vivado:start#installing_digilent_board_files|Installation Instructions]]) can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.+The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 MT/s). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[:vivado:installing-vivado:start#installing_digilent_board_files|Installation Instructions]]) can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.
  
 The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor.  The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, that can be used to clock custom logic implemented in the Programmable Logic (PL). Additionally, the Cora Z7 provides an external 125 MHz reference clock directly to pin H16 of the PL. The external reference clock allows the PL to be used completely independently of the PS, which can be useful for simple applications that do not require the processor. 
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 //Table 13.1.1. Shield Voltage Specifications// //Table 13.1.1. Shield Voltage Specifications//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf|Zynq-7000 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds190-Zynq-7000-Overview|Zynq-7000 datasheet]] from Xilinx.
  
 The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind.
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 ---- ----
-====== Hardware errata ======+===== Hardware errata =====
 Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Cora Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Cora Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
  
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