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programmable-logic:cora-z7:reference-manual [2021/05/14 23:04] – ↷ Page moved from reference:programmable-logic:cora-z7:reference-manual to programmable-logic:cora-z7:reference-manual Arthur Brown | programmable-logic:cora-z7:reference-manual [2023/06/22 21:14] (current) – Arthur Brown | ||
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====== Cora Z7 Reference Manual ====== | ====== Cora Z7 Reference Manual ====== | ||
+ | |||
+ | <WRAP round info> | ||
+ | The Cora Z7-10 variant is now retired in our store. The Cora Z7-07S is not affected and will remain in production. | ||
+ | </ | ||
+ | |||
The Digilent Cora Z7 is a ready-to-use, | The Digilent Cora Z7 is a ready-to-use, | ||
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---- | ---- | ||
- | ====== Features | + | ===== Features ===== |
* **ZYNQ Processor** | * **ZYNQ Processor** | ||
- | * 667MHz | + | * 667MHz |
* FPGA Programmable logic equivalent to Artix-7 FPGA | * FPGA Programmable logic equivalent to Artix-7 FPGA | ||
- | * 4,400 Programmable logic slices (*3,600) | + | * 3,600 Programmable logic slices (*4,400) |
- | * 80 DSP slices (*60) | + | * 60 DSP slices (*80) |
- | * 270 KB of block RAM (*225 KB) | + | * 225 KB of block RAM (*270 KB) |
* DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports | * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports | ||
* High-bandwidth peripheral controllers: | * High-bandwidth peripheral controllers: | ||
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* Programmable from JTAG and microSD card | * Programmable from JTAG and microSD card | ||
* **Memory** | * **Memory** | ||
- | * 512MB DDR3 with 16-bit bus @ 1050Mbps | + | * 512MB DDR3 with 16-bit bus @ 525 MHz (1050 MT/s) |
* microSD slot | * microSD slot | ||
* **Power** | * **Power** | ||
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* 12 additional FPGA Digital I/O | * 12 additional FPGA Digital I/O | ||
- | (*Z7-07S variant in parentheses where different) | + | (*Z7-10 variant in parentheses where different) |
- | {{ cora-z7-callout.png? | + | {{ reference: |
^ Callout | ^ Callout | ||
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| 10 | User push buttons | | 10 | User push buttons | ||
- | ====== Purchasing Options and Board Variants | + | ===== Purchasing Options and Board Variants ===== |
- | The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. | + | A Cora Z7 has either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. |
The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, | The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities, | ||
- | ^ Product Variant | + | ^ Product Variant |
- | ^ Zynq Part | XC7Z010-1CLG400C | + | ^ Zynq Part | XC7Z007S-1CLG400C |
- | ^ ARM Processor Cores | 2 | + | ^ ARM Processor Cores | 1 |
- | ^ 1 MSPS On-chip ADC | Yes | Yes | | + | ^ 1 MSPS On-chip ADC | Yes | Yes |
- | ^ Look-up Tables (LUTs) | + | ^ Look-up Tables (LUTs) |
- | ^ Flip-Flops | + | ^ Flip-Flops |
- | ^ DSP Slices | + | ^ DSP Slices |
- | ^ Block RAM | 270 KB | + | ^ Block RAM | 225 KB |
- | ^ Clock Management Tiles | 2 | 2 | | + | ^ Clock Management Tiles | 2 | 2 |
- | /* | + | |
- | FIXME Optional 5 Volt 4 Amp Power Supply | + | |
- | FIXME Optional Micro USB Cable. | + | For more information on purchasing, see the [[https:// |
- | FIXME Optional microSD Card with Out-of-Box Demonstration Project. | + | /* |
+ | **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[programmable-logic: | ||
*/ | */ | ||
- | For more information on purchasing, see the [[https:// | ||
- | |||
- | **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[: | ||
---- | ---- | ||
- | ====== Software Support | + | ===== Software Support ===== |
The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. | The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. | ||
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Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, | Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information, | ||
- | Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https:// | + | /* Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Cora Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https:// |
---- | ---- | ||
- | ====== Functional Description | + | ===== Functional Description ===== |
===== 1 Power Supplies ===== | ===== 1 Power Supplies ===== | ||
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The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. | The Cora Z7 requires a 5 Volt power source to operate. This power source can come from the Digilent USB-JTAG port (J12) or it can be derived from a 5 Volt DC power supply connected to the Power Jack (J15). Unlike other Digilent FPGAs, the Cora Z7 cannot be powered through the Shield Header. | ||
- | A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http:// | + | A red power-good LED (LD7), driven by the 3.3V output (VCC3V3) of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or [[http:// |
- | {{ cora-power.png? | + | {{ reference: |
//Figure 1.1 Cora Z7 Power Circuit// | //Figure 1.1 Cora Z7 Power Circuit// | ||
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The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, | The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, | ||
- | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, | + | There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, |
Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. | Table 2.1 depicts the external components connected to the MIO pins of the Cora Z7. The Zynq Presets File found on the [[start|Cora Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. | ||
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**Stage 2** | **Stage 2** | ||
- | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/ | + | The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/ |
The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | The Zynq Boot Image is created using Vivado and Xilinx Software Development Kit (Xilinx SDK). For information on creating this image please refer to the available Xilinx documentation for these tools. | ||
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The Cora Z7 supports two different boot modes: microSD and JTAG. The boot mode is selected using the Mode jumper (JP2), which affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the Cora Z7. | The Cora Z7 supports two different boot modes: microSD and JTAG. The boot mode is selected using the Mode jumper (JP2), which affects the state of the Zynq configuration pins after power-on. Figure 3.1 depicts how the Zynq configuration pins are connected on the Cora Z7. | ||
- | {{ cora-config.png? | + | {{ reference: |
//Figure 3.1. Cora Z7 configuration pins.// | //Figure 3.1. Cora Z7 configuration pins.// | ||
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===== 4 DDR3L Memory ===== | ===== 4 DDR3L Memory ===== | ||
- | The Cora Z7 includes a Micron MT41K256M16HA-125 | + | The Cora Z7 includes a single |
+ | |||
+ | **Note:** //The Cora Z7 may use any of the Micron MT41K256M16HA-125, | ||
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. | The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported. | ||
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Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. | Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Cora Z7 memory interface PCB design. | ||
- | For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/ | + | For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/ |
---- | ---- | ||
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===== 6 microSD Slot ===== | ===== 6 microSD Slot ===== | ||
- | The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/ | + | The Cora Z7 provides a microSD slot (J10) for non-volatile external memory storage as well as for booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including the Card Detect signal. On the Zynq PS, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/ |
| **Signal Name** | | **Signal Name** | ||
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The SD slot is powered from the 3.3V rail, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter is used to perform the necessary translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen in Figure 6.1. Mapping out the correct pins and configuring the interface is handled by the Cora Z7 Zynq presets file, available through the [[start|Cora Z7 Resource Center]]. | The SD slot is powered from the 3.3V rail, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter is used to perform the necessary translation. The TXS02612 is actually a 2-port SDIO port expander, but only its level shifter function is used. The connection diagram can be seen in Figure 6.1. Mapping out the correct pins and configuring the interface is handled by the Cora Z7 Zynq presets file, available through the [[start|Cora Z7 Resource Center]]. | ||
- | {{ cora-micro-sd.png? | + | {{ reference: |
//Figure 6.1. microSD slot signals// | //Figure 6.1. microSD slot signals// | ||
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Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. | Both low speed and high speed cards are supported, as the maximum clock frequency is 50 MHz. A Class 4 card or better is recommended. | ||
- | Refer to section 3.1, [[# | + | Refer to section 3.1, [[# |
---- | ---- | ||
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The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. | The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. | ||
- | {{ cora-ethernet.png? | + | {{ reference: |
//Figure 8.1. Ethernet PHY signals// | //Figure 8.1. Ethernet PHY signals// | ||
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On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/ | On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/ | ||
- | For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/ | + | For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/ |
---- | ---- | ||
===== 9 Clock Sources ===== | ===== 9 Clock Sources ===== | ||
- | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: | + | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 MT/s). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: |
The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, | The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, | ||
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Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low. | Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low. | ||
- | {{ cora-z7-clocking.png? | + | {{ reference: |
//Figure 9.1. Cora Z7 Clocking// | //Figure 9.1. Cora Z7 Clocking// | ||
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===== 10 Reset Sources ===== | ===== 10 Reset Sources ===== | ||
- | ==== 10.1 Power-on Reset ==== | + | ==== 10.1 Power-on Reset Signals |
The Zynq Processing System (PS) supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Cora Z7 drives this signal from the nRESET signal of the DA9062 DC-DC converter system in order to hold the system in reset until all power supplies are valid. A push-button, | The Zynq Processing System (PS) supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Cora Z7 drives this signal from the nRESET signal of the DA9062 DC-DC converter system in order to hold the system in reset until all power supplies are valid. A push-button, | ||
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The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are “momentary” switches that normally generate a low output when they are at rest, and a high output only when they are pressed. | The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are “momentary” switches that normally generate a low output when they are at rest, and a high output only when they are pressed. | ||
- | {{ cora-basic-io.png? | + | {{ reference: |
//Figure 11.1. Cora Z7 Basic I/O// | //Figure 11.1. Cora Z7 Basic I/O// | ||
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Figure 13.1 diagrams the pins found on the shield connector of the Cora Z7. | Figure 13.1 diagrams the pins found on the shield connector of the Cora Z7. | ||
- | {{ cora-shield.png? | + | {{ reference: |
//Figure 13.1. Shield connector pin diagram.// | //Figure 13.1. Shield connector pin diagram.// | ||
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//Table 13.1.1. Shield Voltage Specifications// | //Table 13.1.1. Shield Voltage Specifications// | ||
- | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://www.xilinx.com/ | + | For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/ |
The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. | The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. On the Cora Z7, these signals are each attached to a pull-up resistor. While these pins can still be used as digital I/O, these pull-ups should be kept in mind. | ||
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The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Cora Z7's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as digital inputs or outputs, as they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 13.2.1). | The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Cora Z7's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as digital inputs or outputs, as they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 13.2.1). | ||
- | {{ cora-analog-single-ended.png? | + | {{ reference: |
//Figure 13.2.1. Single-Ended Analog Inputs// | //Figure 13.2.1. Single-Ended Analog Inputs// | ||
The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 13.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even-numbered pins are connected to the positive pins of the trio and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. | The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 13.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even-numbered pins are connected to the positive pins of the trio and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. | ||
- | {{ cora-analog-differential.png? | + | {{ reference: |
//Figure 13.2.2. Differential Analog Inputs// | //Figure 13.2.2. Differential Analog Inputs// | ||
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 13.2.3 for this pair of pins is loaded on the Cora Z7. | The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 13.2.3 for this pair of pins is loaded on the Cora Z7. | ||
- | {{ cora-analog-dedicated.png? | + | {{ reference: |
//Figure 13.2.3. Dedicated Analog Input Pair// | //Figure 13.2.3. Dedicated Analog Input Pair// | ||
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The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can be found in the Cora Z7 master XDC file, available through the [[start|Cora Z7 Resource Center]]. | The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can be found in the Cora Z7 master XDC file, available through the [[start|Cora Z7 Resource Center]]. | ||
- | {{ cora-unloaded-header.png? | + | {{ reference: |
//Figure 14.1. Unloaded Expansion Header// | //Figure 14.1. Unloaded Expansion Header// | ||
---- | ---- | ||
- | ====== Hardware errata | + | ===== Hardware errata ===== |
Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. | Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below. | ||
^ Product Name ^ Variant | ^ Product Name ^ Variant | ||
- | | Cora Z7 | All | All | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado > | + | | Cora Z7 | All | All | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado > |
{{tag>rm doc cora-z7}} | {{tag>rm doc cora-z7}} |