Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revision | |||
programmable-logic:cora-z7:reference-manual [2023/05/12 19:00] – [4 DDR3L Memory] Arthur Brown | programmable-logic:cora-z7:reference-manual [2023/06/22 21:14] (current) – Arthur Brown | ||
---|---|---|---|
Line 32: | Line 32: | ||
* Programmable from JTAG and microSD card | * Programmable from JTAG and microSD card | ||
* **Memory** | * **Memory** | ||
- | * 512MB DDR3 with 16-bit bus @ 1050Mbps | + | * 512MB DDR3 with 16-bit bus @ 525 MHz (1050 MT/s) |
* microSD slot | * microSD slot | ||
* **Power** | * **Power** | ||
Line 361: | Line 361: | ||
===== 9 Clock Sources ===== | ===== 9 Clock Sources ===== | ||
- | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: | + | The Cora Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the Processing System (PS) subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 MT/s). The Cora Z7 Zynq Preset file available within the Digilent Vivado Board File package ([[: |
The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, | The PS has a dedicated Phase-Locked Loop (PLL) capable of generating up to four reference clocks, each with settable frequencies, |