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learn:software:tutorials:verilog-project-2:start [2017/01/25 20:31] – James Colvin | learn:software:tutorials:verilog-project-2:start [2022/09/08 20:38] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey | ||
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===== Project Overview ===== | ===== Project Overview ===== | ||
- | The goal of this project is to take the [[learn/ | + | The goal of this project is to take the [[learn/ |
A list of the previous projects can be found [[learn/ | A list of the previous projects can be found [[learn/ | ||
- | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/ | + | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/ |
===== Some Background Information ===== | ===== Some Background Information ===== | ||
- | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' | + | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' |
===== Relooking at the Simple Example HDL ===== | ===== Relooking at the Simple Example HDL ===== | ||
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===== Programming our FPGA ===== | ===== Programming our FPGA ===== | ||
- | > 0) If you haven' | + | > 0) If you haven' |
> 1) On the opening screen, click on the '' | > 1) On the opening screen, click on the '' | ||
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> | > | ||
- | > 7) After clicking next on the IP cores since we don't have any to add, click '' | + | > 7) After clicking next on the IP cores since we don't have any to add, click '' |
> | > | ||
> | > | ||
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> | > | ||
- | > 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there' | + | > 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there' |
> | > | ||
> | > | ||
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> | > | ||
- | You'll then be asked to choose the bitstream file (we don't have a debug core in our code, so we won't put anything in that field) | ||
> 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field. | > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field. | ||
> | > | ||
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Now we're done! The way this project was setup, the first switch (labeled '' | Now we're done! The way this project was setup, the first switch (labeled '' | ||
- | insert a picture of this working here FIXME :!: | + | {{:learn:software: |
- | + | ||
- | also need to fix images 15, 26, and 27 to have the module be called '' | + | |
==== Multiple Switches and LEDs ==== | ==== Multiple Switches and LEDs ==== | ||
But why restrict ourselves to a single input and a single output? Perhaps instead we want create a '' | But why restrict ourselves to a single input and a single output? Perhaps instead we want create a '' | ||
- | As I am using the [[http://store.digilentinc.com/ | + | As I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/ |
This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. | This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. | ||
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> | > | ||
- | > 2) Once the corresponding Verilog module has been created, we can '' | + | > 2) Once the corresponding Verilog module has been created, we can '' |
> | > | ||
> | > | ||
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> | > | ||
- | > 4) Here' | + | > 4) Here' |
+ | > | ||
+ | > {{learn: | ||
+ | |||
+ | > 5) It is also possible to assign a bus of outputs the value of a bus of inputs. The trick here is that you need to use the bit-wise negation operator, '' | ||
+ | > | ||
+ | > {{learn: | ||
+ | |||
+ | > 6) Here's what the Arty looks like for the above code with SW3 switched " | ||
> | > | ||
- | >FIXME need image | + | > {{learn: |
- | > 5) It is also possible to assign a bus of outputs | + | ==== Taking it one step further ==== |
+ | Try using some of the external I/O rather than the embedded I/O on your system board. You can even keep the Verilog module code exactly the same; the key here will be to change the XDC file so that the pins you want to use instead (such as some Pmod Host port pins) match the names used in your port declarations in your Verilog module. | ||
===== Important Takeaways from Project 2 ===== | ===== Important Takeaways from Project 2 ===== | ||
- | * | + | * Creating single bit and multi-bit inputs and outputs |
+ | * Assigning input ports to output ports for single bits, bits within bus's, and bus's to bus' | ||
+ | * Confidence in going through the Vivado design flow from creating a project, editing it, and programming the system board | ||
- | tags to be added after I add in curly braces in the code below\\ | ||
- | '' |