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learn:software:tutorials:verilog-project-2:start [2017/01/25 17:35] – James Colvinlearn:software:tutorials:verilog-project-2:start [2022/09/08 20:38] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey
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 ===== Project Overview ===== ===== Project Overview =====
-The goal of this project is to take the [[learn/software/tutorials/verilog-project-1/start#A_simple_Example|simple example from Project 1]] and program our FPGA with it so that we can control a single LED with a single switch. Then, we'll take the same program and expand it to have multiple switches control multiple LEDs. Brave users will be challenged (with some guidance) at the end to do the same thing with some external components. If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]].+The goal of this project is to take the [[learn/software/tutorials/verilog-project-1/start#A_simple_Example|simple example from Project 1]] and program our FPGA with it so that we can control a single LED with a single switch. Then, we'll take the same program and expand it to have multiple switches control multiple LEDs. Brave users will be challenged at the end to do the same thing with some external components. If you have not already installed Vivado, you can find a guide to do so [[learn/software/tutorials/vivado-install-guide/start|here]]. If you are hoping for a Project 0 where you learn how to navigate the Vivado interface in the first place, we highly recommend the [[vivado/getting_started/start|Getting Started with Vivado Guide]].
  
 A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]]. A list of the previous projects can be found [[learn/software/tutorials/verilog-projects/start|here]].
  
-//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//+//This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/system-boards/|Digilent system boards]]. However, the project can be easily modified to accommodate different types of external inputs (buttons instead of switches) or to use external I/O components rather than embedded components. If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilent.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
 ===== Some Background Information =====  ===== Some Background Information ===== 
-The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[learn/software/tutorials/vivado-xdc-file|XDC file]]) +The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, '1', or logic low, '0'. The input is then passed directly to an embedded LED that shows the corresponding logic by being "on" (a logic high) or "off" (a logic low). Both the embedded switch and LED are connected to their own ports on the FPGA and are specified in the constraint file (for Vivado, this is the [[programmable-logic:guides:vivado-xdc-file|XDC file]]) 
  
 ===== Relooking at the Simple Example HDL =====  ===== Relooking at the Simple Example HDL ===== 
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 ===== Programming our FPGA ===== ===== Programming our FPGA =====
  
-> 0) If you haven't already done so, go ahead and open up Vivado to the first screen and click on the "Create New Project" button. If you've gone through the [[vivado/getting_started/start|Getting Started with Vivado Guide]] already, a lot of this will be very familiar to you (or near identical). You can follow along if you like, or if you feel that you can get your board programmed by yourself without the guide, feel free to do so (just to confirm you've got it right), and then [[:learn:software:tutorials:verilog-project-2:start#multiple_switches_and_LEDS|jump down]] to the multiple switches and LEDs section.+> 0) If you haven't already done so, go ahead and open up Vivado to the first screen and click on the "Create New Project" button. If you've gone through the [[vivado/getting_started/start|Getting Started with Vivado Guide]] already, a lot of this will be very familiar to you (or near identical). You can follow along if you like, or if you feel that you can get your board programmed by yourself without the guide, feel free to do so (just to confirm you've got it right), and then __[[:learn:software:tutorials:verilog-project-2:start#multiple_switches_and_LEDS|jump down]]__ to the multiple switches and LEDs section.
  
 > 1) On the opening screen, click on the ''Create New Project'' button. > 1) On the opening screen, click on the ''Create New Project'' button.
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 >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:create_the_source_file.png?600|Create the source file (click to enlarge)}}
  
-> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[learn/software/tutorials/vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/|Arty]], I used the Master XDC available on it's [[reference/programmable-logic/arty/start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.+> 7) After clicking next on the IP cores since we don't have any to add, click ''Add Files'' on the Add Constraints page. Digilent boards have a master [[programmable-logic:guides:vivado-xdc-file|XDC]] (Xilinx Design Constraints) file available on their Wiki pages. Since I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty]], I used the Master XDC available on it's [[programmable-logic:arty:start|Resource Center]] on the right hand side under "Design Resources" and saved mine to a convenient location on my computer.
 > >
 >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:add_our_constraint_file.png?600|Add our constraint file (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_the_verilog_module_now.png?600|Let's edit the Verilog module (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_the_verilog_module_now.png?600|Let's edit the Verilog module (click to enlarge)}}
  
-> 15) Now we just need to add the functionality of how our circuit module we are creating on the FPGA that has a single input and a single output is going to work. This is done between the ''};'' in the module declaration(instantiation :?:) and the keyword ''endmodule''. For this project, we just want to have the state of the output (the LED) be the same as the state of the input (the switch), so we will use an ''assign'' statement to assign the state of the LED to be equal to the state of the switch via the following line of code:+> 15) Now we just need to add the functionality of how our circuit module we are creating on the FPGA that has a single input and a single output is going to work. This is done by declaring our inputs and outputs between the ''};'' in the module and the keyword ''endmodule''. For this project, we just want to have the state of the output (the LED) be the same as the state of the input (the switch), so we will use an ''assign'' statement to assign the state of the LED to be equal to the state of the switch via the following line of code:
 >''assign led = sw;'' >''assign led = sw;''
 > Press Cntl+S to save your changes. > Press Cntl+S to save your changes.
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 >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:find_our_constraints_file.png?600|Where is the Vivado constraints file (click to enlarge)}}
  
-> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[learn/software/tutorials/vivado-xdc-file|XDC file here]].+> 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there's a lot of lines of text so we want to only uncomment the pins we are using and change the name of the pin to match the names of our inputs and outputs on our top module. You can learn some more details about a [[programmable-logic:guides:vivado-xdc-file|XDC file here]].
 > >
 >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:we_can_edit_our_constraints_file_now.png?600|Let's edit our constraints (click to enlarge)}}
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 >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}} >{{:learn:software:tutorials:verilog-project-2:choose_auto_connect.png?600|Auto connect to your FPGA after it is connected (click to enlarge)}}
  
-You'll then be asked to choose the bitstream file (we don't have a debug core in our code, so we won't put anything in that field) 
 > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field. > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field.
 > >
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 Now we're done! The way this project was setup, the first switch (labeled ''SW0'' on the Arty) controls the status of the first LED (labeled ''LD4'' on the Arty). Now we're done! The way this project was setup, the first switch (labeled ''SW0'' on the Arty) controls the status of the first LED (labeled ''LD4'' on the Arty).
  
-insert a picture of this working here FIXME :!: +{{:learn:software:tutorials:verilog-project-2:switch_to_led_demo.png?600|An image of the above demo in action (click to enlarge)}}
- +
-also need to fix images 15, 26, and 27 to have the module be called ''led_sw'' instead of top+
  
 ==== Multiple Switches and LEDs ==== ==== Multiple Switches and LEDs ====
 But why restrict ourselves to a single input and a single output? Perhaps instead we want create a ''bus'' of inputs and outputs (like an array in a C/C++ environment) so we can try out some more complex (but still simple) combinatorial logic. But why restrict ourselves to a single input and a single output? Perhaps instead we want create a ''bus'' of inputs and outputs (like an array in a C/C++ environment) so we can try out some more complex (but still simple) combinatorial logic.
  
-As I am using the [[http://store.digilentinc.com/arty-artix-7-fpga-development-board-for-makers-and-hobbyists/|Arty board]] which has four embedded switches and four mono-color LEDs (as well as four tri-color LEDs if I want to use them) I will be using a 4-bit bus for my inputs and outputs. Your FPGA board may have a different number or a different type of available inputs and outputs, or perhaps you need to use some external components to get some physical inputs and outputs. We won't be going through every step like we did the first time, although some key screenshots will be shown as a reference point for your convenience. //Remember, If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilentinc.com/|Digilent Forum]] where an engineer will be happy to assist you.//+As I am using the [[https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/|Arty board]] which has four embedded switches and four mono-color LEDs (as well as four tri-color LEDs if I want to use them) I can easily use up to a 4-bit bus for my inputs and outputs. Your FPGA board may have a different number or a different type of available inputs and outputs, or perhaps you need to use some external components to get some physical inputs and outputs. If I took advantage of some external components, I could theoretically create as large of a bus as I wanted, but that is beyond the scope of this project.  We won't be going through every step like we did the first time, although some key screenshots will be shown as a reference point for your convenience. //Remember, If you have any questions after reading through the project, please feel free to post them on the [[https://forum.digilent.com/|Digilent Forum]] where an engineer will be happy to assist you.//
  
-probably three different portions of this: the 1 to 1 ratio, the 1 to 1 with some NOT's incorporated, and bus to bus with some binary incorporated. +This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions.  
 + 
 +> 1) The same process of a creating a Vivado project was followed; a top module was created, no IP was added, and the Master XDC file was copied into the local directory. Once we confirm our project settings, we can then create our new module with buses on the module wizard that appears. For each input or output that you want to be a bus, check the ''bus'' box and indicate the size of the bus through the ''MSB'' and ''LSB'' options. 
 +> 
 +>{{:learn:software:tutorials:verilog-project-2:creating_a_module_with_a_bus.png?600|Creating a bus through the module wizard (click to enlarge)}} 
 + 
 +> 2) Once the corresponding Verilog module has been created, we can ''assign'' individual values within each bus to other individual values. As you might expect, you cannot ''assign'' a whole bus to a single input or output, but can perform some logical operations, such as the logical negation or ''!'' operator. 
 +>  
 +>{{:learn:software:tutorials:verilog-project-2:assigning_individual_values_in_a_bus.png?600|Assign individual values inside of a bus (click to enlarge)}} 
 + 
 +> 3) The XDC file will also need to be edited so that Vivado knows which FPGA pins we intend to use. With this Master XDC file, the names of the pins for both the switches (shown) and the LEDs (not shown in the image) are already named in such a way so that they match the names used in our Verilog module. You could change the names in both the module and the XDC file to something else, but why do more work if it is already legible? 
 +> 
 +>{{:learn:software:tutorials:verilog-project-2:part_of_the_xdc_file_for_our_bus_inputs.png?600|What part of the XDC file will look like for the bus inputs and outputs (click to enlarge)}} 
 + 
 +> 4) Here's what the Arty looks like with SW0 switched "on" and SW1 switched "off". 
 +> 
 +> {{learn:software:tutorials:verilog-project-2:2-bit_bus_demo.png?600|Image of the above demo in action (click to enlarge)}} 
 + 
 +> 5) It is also possible to assign a bus of outputs the value of a bus of inputs. The trick here is that you need to use the bit-wise negation operator, ''~'', rather than the logical negation operator, ''!'', which operates on the entire bus rather than bit by bit. The ''~'' operator will also work for single bits much like the example immediately above this one. 
 +> 
 +> {{learn:software:tutorials:verilog-project-2:bus_to_bus_module.png?600|Verilog Module assigning a bus of LEDs to the opposite state of a bus of switches (click to enlarge)}} 
 + 
 +> 6) Here's what the Arty looks like for the above code with SW3 switched "off" and switches SW0, SW1, and SW2 switched "on". 
 +> 
 +> {{learn:software:tutorials:verilog-project-2:bus_to_bus_demo.png?600|Image of the above demo in action (click to enlarge)}}
  
-{{:learn:software:tutorials:verilog-project-2:assigning_individual_values_in_a_bus.png?600|Assign individual values inside of a bus (click to enlarge)}}\\ +==== Taking it one step further ==== 
-{{:learn:software:tutorials:verilog-project-2:part_of_the_xdc_file_for_our_bus_inputs.png?600|What part of the XDC file will look like for the bus inputs and outputs (click to enlarge)}}\\ +Try using some of the external I/O rather than the embedded I/O on your system board. You can even keep the Verilog module code exactly the same; the key here will be to change the XDC file so that the pins you want to use instead (such as some Pmod Host port pins) match the names used in your port declarations in your Verilog module.
-{{:learn:software:tutorials:verilog-project-2:creating_a_module_with_a_bus.png?600|Creating a bus through the module wizard (click to enlarge)}}+
  
 ===== Important Takeaways from Project 2 ===== ===== Important Takeaways from Project 2 =====
-  * +  * Creating single bit and multi-bit inputs and outputs 
 +  * Assigning input ports to output ports for single bits, bits within bus's, and bus's to bus's 
 +  * Confidence in going through the Vivado design flow from creating a project, editing it, and programming the system board
  
-tags to be added after I add in curly braces in the code below\\ 
-''tag> learn programmable-logic software tutorials vivado verilog''