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learn:software:tutorials:verilog-project-2:start [2017/01/17 02:10] – [Some Background Information] James Colvin | learn:software:tutorials:verilog-project-2:start [2022/09/08 20:38] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey | ||
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====== Verilog® HDL: Project 2 ====== | ====== Verilog® HDL: Project 2 ====== | ||
+ | |||
===== Using switches to control LEDs ===== | ===== Using switches to control LEDs ===== | ||
===== Project Overview ===== | ===== Project Overview ===== | ||
- | The goal of this project is to take the [[learn/ | + | The goal of this project is to take the [[learn/ |
A list of the previous projects can be found [[learn/ | A list of the previous projects can be found [[learn/ | ||
- | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[http://store.digilentinc.com/fpga-programmable-logic/ | + | //This project presumes you are using an FPGA development board that has external slide switches and LEDs built into the board, much like the [[https://digilent.com/shop/boards-and-components/ |
===== Some Background Information ===== | ===== Some Background Information ===== | ||
- | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' | + | The digital circuit we are building from Project 1 is called led_sw. With this project, the FPGA is receiving an input signal, in this case from an embedded switch, that can be logic high, ' |
===== Relooking at the Simple Example HDL ===== | ===== Relooking at the Simple Example HDL ===== | ||
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But enough with the review, let's make our project! | But enough with the review, let's make our project! | ||
- | ==== Programming our FPGA ==== | + | ===== Programming our FPGA ===== |
- | If you haven' | + | |
- | On the opening | + | > 0) If you haven' |
- | {{: | + | |
- | You'll then encounter some friendly instructions from Xilinx | + | > 1) On the opening screen, click on the '' |
- | {{: | + | > |
+ | >{{: | ||
- | Here, we' | + | > 2) You' |
- | {{: | + | > |
+ | >{{: | ||
- | Choose create a RTL (Register Transfer Level) project and keep the box unchecked | + | > 3) Here, we'll name our project and choose where to save our project file on our computer. It is critical that no spaces are used in either the name of the project or the file path that project is saved in; Vivado notoriously has problems with spaces, so using underscores or [[https:// |
- | {{: | + | > |
+ | >{{: | ||
- | Click " | + | > 4) Choose create a RTL (Register Transfer Level) project and keep the box unchecked so that we can specify sources for our project. Click '' |
- | {{: | + | > |
+ | >{{: | ||
- | In the window that pops up, keep the file type as Verilog and name your Verilog module. | + | > 5) Click '' |
- | {{: | + | > |
+ | >{{: | ||
- | After clicking next on the IP cores since we don't have any to add, click "Add Files" on the Add Constraints page. Digilent boards have a master XDC (Xilinx Design Constraints) | + | > 6) In the window that pops up, keep the file type as Verilog and name your Verilog module. A commonly used name for modules, especially ones that call and use other modules, is " |
- | {{: | + | > |
+ | >{{: | ||
- | You'll get the opportunity | + | > 7) After clicking next on the IP cores since we don't have any to add, click '' |
- | {{: | + | > |
+ | >{{: | ||
- | Make sure you have the "Copy constraints files into project" | + | > 8) You'll get the opportunity to browse to your XDC file, which I happened to save in a folder that I named VivadoXDCfiles. Click '' |
- | {{: | + | > |
+ | >{{: | ||
- | Here you will want to select | + | > 9) Make sure you have the '' |
- | {{: | + | > |
- | {{: | + | >{{: |
- | Confirm | + | > 10) Here you will want to select the FPGA that you are using to ensure that Vivado designs and programs the hardware correctly. You can either search by FPGA part number from the '' |
- | {{: | + | > |
+ | > | ||
+ | > 11) Confirm that your project has what you want to have (at least initially) and click " | ||
+ | > | ||
+ | > | ||
- | {{: | + | > 12) After a brief loading, we are presented with a top module wizard (since we said we were creating our own source file called " |
+ | > | ||
+ | >{{: | ||
- | {{: | + | > 13) Now we are finally at the main Vivado GUI where we can edit our source and constraint files and eventually program the FPGA. Double click on our Verilog module called (in my case) " |
+ | > | ||
+ | >{{: | ||
- | {{: | + | > 14) Our Verilog module will appear in the upper left window known as the workspace. It comes prefilled with some Verilog code including the required timescale, a nice comments section for documentation purposes, our named module with the inputs and outputs we created in the wizard, and the '' |
+ | > | ||
+ | >{{: | ||
- | verilog | + | > 15) Now we just need to add the functionality of how our circuit |
- | {{: | + | >'' |
+ | > Press Cntl+S to save your changes. | ||
+ | > | ||
+ | >{{: | ||
- | find our constraints file | ||
- | {{: | ||
- | edit our constraints file with link to page on XDC files | + | > 16) Now we' |
- | {{: | + | > |
+ | >{{: | ||
- | {{: | + | > 17) Our XDC will become visible in the workspace window (as mentioned in the step above). As this is a master XDC file (at least for me) there' |
+ | > | ||
+ | >{{: | ||
- | click run synthesis, | + | > 18) The two lines I will uncomment in this project will be the line corresponding to the first switch (labeled SW0 on the silk screen of the Arty) and the line corresponding to the first mono-color LED (labeled LD4 on the silk screen of the Arty). I renamed the switch (pin A8 on the FPGA) to sw and renamed the LED (pin H5 on the FPGA) to led. Press Cntr+S to save your changes. |
- | {{: | + | > |
+ | >{{: | ||
- | choose synthesis options; This can take awhile since Vivado processes a ton of things hidden to the user and works with the entire FPGA and not just what we are utilizing, so you'll probably want to maximize | + | > 19) Click the ''Run Synthesis'' |
- | {{: | + | > |
+ | >{{: | ||
- | synthesis | + | > 20) A wizard will pop up that will allow you to choose your synthesis |
- | {{: | + | > As a side note, the whole combination of synthesis, implementation, |
+ | > When you are happy with your selections, click '' | ||
+ | > | ||
+ | >{{: | ||
- | click run implementation on the wizard that pops up, can choose how many cores you use again if you haven't clicked | + | > 21) After you click ok, you'll need to wait for the synthesis to finish running, which may take a minute or two depending on how fast your computer runs. |
- | {{: | + | > |
+ | >{{: | ||
- | implementation running | + | > 21) Click '' |
- | {{: | + | > |
+ | >{{: | ||
- | click generate bitstream on the wizard (don't necessarily want to click the " | + | > 22) After you click ok, you'll need to wait for the implementation to finish running, which may take a minute |
- | {{: | + | > |
+ | >{{: | ||
- | generate bitstream | + | > 23) Another wizard will pop up where you will want to click '' |
- | {{: | + | > As a side note, you may not necessarily want to click the '' |
+ | > After this screen you will be able to choose some bitstream generation options, much like for synthesis and implementation. When you are happy with your selections, click '' | ||
+ | > | ||
+ | >{{: | ||
- | click open hardware manager on the wizard and then click ok. | + | > 24) After you click ok, you'll need to wait for the bitstream generation to finish running, which may take a minute or two depending on how fast your computer runs. |
- | {{: | + | > |
+ | >{{: | ||
- | if your FPGA is not connected already, you'll see a "no hardware target is open" message at the top. | + | > 25) Click ''Open Hardware Manager'' |
- | {{: | + | > |
+ | >{{: | ||
- | You'll be able to click the "open target" | + | > 26) If your FPGA is not connected |
- | {{: | + | > |
+ | >{{: | ||
- | You'll then be asked to choose the bitstream file (we don't have a debug core in our code, so we won't put anything in that field) | + | > 27) Make sure your FPGA is connected |
- | {{: | + | > |
+ | >{{: | ||
- | The bitstream file itself is a little unintuitive to find. You can find it by opening up the folder where you told Vivado | + | > 28) You'll then be asked to choose the bitstream file that we are to program the FPGA with; we don't have a debug core in our code, so we won't have to put anything in that field. |
- | {{: | + | > |
+ | >{{: | ||
- | click program; this takes under 10 seconds for any computer, so it's not too bad. | + | > 29) The bitstream file itself is a little unintuitive to find. You can find it by opening up the folder where you told Vivado to initially save your project, go to ''< |
- | {{: | + | > |
+ | > | ||
+ | |||
+ | > 30) Finally, we can click '' | ||
+ | > | ||
+ | >{{: | ||
Now we're done! The way this project was setup, the first switch (labeled '' | Now we're done! The way this project was setup, the first switch (labeled '' | ||
- | + | {{: | |
- | really need to create the XDC file page to talk about that\\ | + | |
- | also need to get a set of pictures of how to program | + | |
==== Multiple Switches and LEDs ==== | ==== Multiple Switches and LEDs ==== | ||
+ | But why restrict ourselves to a single input and a single output? Perhaps instead we want create a '' | ||
+ | |||
+ | As I am using the [[https:// | ||
+ | |||
+ | This tutorial presumes that you created a new project to for the bus inputs and outputs, but you can easily modify your existing project to accept these additions. | ||
+ | |||
+ | > 1) The same process of a creating a Vivado project was followed; a top module was created, no IP was added, and the Master XDC file was copied into the local directory. Once we confirm our project settings, we can then create our new module with buses on the module wizard that appears. For each input or output that you want to be a bus, check the '' | ||
+ | > | ||
+ | > | ||
+ | |||
+ | > 2) Once the corresponding Verilog module has been created, we can '' | ||
+ | > | ||
+ | > | ||
+ | |||
+ | > 3) The XDC file will also need to be edited so that Vivado knows which FPGA pins we intend to use. With this Master XDC file, the names of the pins for both the switches (shown) and the LEDs (not shown in the image) are already named in such a way so that they match the names used in our Verilog module. You could change the names in both the module and the XDC file to something else, but why do more work if it is already legible? | ||
+ | > | ||
+ | > | ||
+ | |||
+ | > 4) Here's what the Arty looks like with SW0 switched " | ||
+ | > | ||
+ | > {{learn: | ||
+ | |||
+ | > 5) It is also possible to assign a bus of outputs the value of a bus of inputs. The trick here is that you need to use the bit-wise negation operator, '' | ||
+ | > | ||
+ | > {{learn: | ||
+ | |||
+ | > 6) Here's what the Arty looks like for the above code with SW3 switched " | ||
+ | > | ||
+ | > {{learn: | ||
- | //The above assign statement gives the current value of sw (switch) to led (an LED). | + | ==== Taking it one step further ==== |
- | //Because HDL in general (not just Verilog) describes an actual circuit that will | + | Try using some of the external I/O rather than the embedded I/O on your system board. You can even keep the Verilog module code exactly the same; the key here will be to change |
- | //be implemented onto the FPGA, rather than telling a processor what to do like in | + | |
- | //a microcontroller which is limited by its internal clock that dictates | + | |
- | //the above statement that assigns | + | |
- | //in real time, or at least as fast as it takes the electricity | + | |
- | //the switch to the FPGA and then directly | + | |
===== Important Takeaways from Project 2 ===== | ===== Important Takeaways from Project 2 ===== | ||
- | * | + | * Creating single bit and multi-bit inputs and outputs |
+ | * Assigning input ports to output ports for single bits, bits within bus's, and bus's to bus' | ||
+ | * Confidence in going through the Vivado design flow from creating a project, editing it, and programming the system board | ||
- | tags to be added via the tag> and double curly braces around everything\\ | ||
- | learn programmable-logic software tutorial vivado verilog |