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- 2-bit_bus_demo.png
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- 2017/01/27 19:00
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- add_our_constraint_file.png
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- assigning_individual_values_in_a_bus.png
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- bitstream_file_location.png
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- bus_to_bus_module.png
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- choose_auto_connect.png
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- confirm_your_project.png
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- copy_constraint_files_into_project.png
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- create_an_rtl_project_with_sources.png
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- friendly_instructions_for_creating_a_new_project.png
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- verilog_module_is_edited.png
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- we_can_edit_our_constraints_file_now.png
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- we_can_edit_the_verilog_module_now.png
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![[root]](https://digilent.com/reference/learn/software/tutorials/verilog-project-2/start?ns=&tab_files=files&do=media&tab_details=view&image=learn%3Asoftware%3Atutorials%3Averilog-project-2%3Acreate_an_rtl_project_with_sources.png){kind=link}
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- Date:
- 2017/01/11 20:49
- Filename:
- create_an_rtl_project_with_sources.png
- Format:
- PNG
- Size:
- 124KB
- Width:
- 925
- Height:
- 666
- References for:
- Verilog® HDL: Project 2