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learn:software:tutorials:digilent-core-install:start [2017/03/28 18:49] – created Thomas Kappenmanlearn:software:tutorials:digilent-core-install:start [2017/08/07 19:49] (current) – [1. Adding the board manager URL] Martha
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 ====== Installing the Digilent Core for Arduino ====== ====== Installing the Digilent Core for Arduino ======
  
-{{:learn:software:tutorials:digilent-core-install:bmx3oncom6.jpg?400|}} +This guide will provide a step by step walk-through of installing the Digilent Core on Arduino (Windows/Mac/Linux). This will install the board files, compilers, and programmers necessary to program Digilent PIC32 boards using Arduino.
- +
- +
-===== Overview ===== +
-This guide will provide a step by step walk-through of installing the Digilent Core on Arduino. This will install the board files, compilers, and programmers necessary to program Digilent PIC32 boards using Arduino. +
- +
  
 ----- -----
- 
  
 ===== Prerequisites ===== ===== Prerequisites =====
- 
-===Skills=== 
-  * **Familiarity with soldering** FIXME 
-    * //Some more info// 
-  * **Karate Skills** FIXME 
-    * //Blackbelt recommended// 
- 
-===Hardware=== 
-  * **Board** FIXME 
-  * **Micro-USB cable** 
-  * **Power Supply**  
  
 ===Software=== ===Software===
-  * **Vivado 201X.X** FIXME  +  * **Arduino 1.6.9**  
-    * Newer/older versions can be used, but the procedure may vary slightly. Follow the **[[learn:software:tutorials:vivado-install-guide:start|Vivado Installation]]** guide to learn how to install Vivado +    * [[https://www.arduino.cc/en/Main/OldSoftwareReleases#previous | Version 1.6.9 is highly recommended]]. The newer versions have introduced complications with file inclusions, and may not be compatible with the Digilent Core. 
-  * **Vivado Board Support Files**  +  * **Note:** If you have version 1.0.1 or earlier installed, you will need to first delete the "xc32-tools-Digilent-master-win.zip" located at: 
-    * Follow the **[[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]** guide to learn how to install Board Support Files for Vivado +    * **Windows** - %LocalAppData%\Arduino15\staging\packages  
- +    * **Mac** - /Users/<USERNAME>/Library/Arduino15/staging/packages
- +
 ----- -----
  
- 
-**This Template is taken from the Genesys2 guide. Use this as a template, but make your own pictures when choosing boards and showing the block designs.** 
  
 =====Tutorial===== =====Tutorial=====
  
  
-====1. Creating the Project====+====1. Adding the board manager URL ====
  
->1.1) Click on **Create New Project**. Choose the Project Name and Location such that there are **no blank spaces**. This is an important naming convention to follow for project names, file names and location paths.   +>1.1) **Open** Arduino and click **File>>Preferences**.
->Underscore in a good substitute for empty spaces.+
 > >
->It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.+>Copy and paste the following URL into the "Additional Boards Manager URLs" box. 
 +>https://s3-us-west-2.amazonaws.com/digilent/Software/Digilent_Core/package_digilent_index.json
 > >
->Name your Project and select the Project location and click **Next**. +>Click OK when finished.
 > >
->{{:genesys2:gsmbs1.jpg?nolink&500|}}+>{{:learn:software:tutorials:digilent-core-install:boardurl.jpg?nolink&500|}}
  
  
->1.2) Choose Project Type as **RTL Project**. Leave the - do not specify sources box unchecked and click **Next**.+>1.2) Click **Tools>Board>Boards Manager...** to open the Arduino boards manager.
 > >
->{{:basys3:basys3_screen_shot_2015-6-10_3.png?nolink&500|}}+>{{:learn:software:tutorials:digilent-core-install:board_manager.jpg?nolink&500|}}
  
->1.3) We will not be importing or creating any files here, so click **Next** until the part select screen.+>1.3) Scroll to the bottom and click the **Install** button for the Digilent Core to install it.
 > >
->{{:basys3:1.png?nolink&200|}}{{:basys3:2.png?nolink&200|}}{{:basys3:3.png?nolink&200|}}+>{{:learn:software:tutorials:digilent-core-install:board_manager2.jpg?nolink&500|}}
  
->1.4) If you have completed the **[[vivado:boardfiles|Board Support File Wiki guide]]**, select **Boards**. +>1.4) Once it has finished installing, the Digilent boards can be selected in the **Tools>Board** menu.
->Genesys2 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Select the **Genesys2** and click **Next**.+
 > >
->{{:genesys2:pg6.jpg?nolink&500|}}+>{{:learn:software:tutorials:digilent-core-install:boards.jpg?nolink&500|}}
  
->1.5) A summary of the new project design sources and target device is displayed. Click **Finish**. +{{tag>digilent-core tutorial basys-mx3 pmod }}
-> +
->{{:genesys2:gsmb2.jpg?nolink&500|}} +
- +
------ +
- +
-====2. Creating New Block Design ==== +
- +
-This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. +
- +
-For our design, we will use the IP Integrator to create a new block design. +
- +
-{{:genesys2:gsmb3.jpg?nolink&800|}} +
- +
->2.1) On the left you should see the Flow Navigator. Select **Create Block Design** under the IP Integrator. Give a name to your design (without any empty spaces) and click **Ok**. +
-> +
->{{:genesys2:gsmb4.jpg?nolink&500|}} +
-> +
->You have created a new block design. +
-> +
->{{:genesys2:gsmb5.jpg?nolink&500|}} +
- +
------ +
- +
-====3. Adding the DDR3 Component==== +
- +
->3.1) Click the **Board** tab (Highlighted in orange below) +
-> +
->{{:genesys2:gsmb7.jpg?nolink&700|}} +
-> +
->This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs. +
- +
->3.2) Click and drag the **DDR3 SDRAM** component onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and system clock to the MIG IP. +
-> +
->{{:genesys2:gsmb8.jpg?nolink&500|}} +
- +
- +
->3.3) Click **Run Connection Automation** in the green banner above. Click **Ok**. +
-> +
->{{:genesys2:gsmb9.jpg?nolink&500|}} +
-> +
->Vivado will connect your system reset to sys_rst on the MIG. +
- +
------ +
- +
-====4. Adding the Microblaze Processor & Configuration ==== +
- +
->4.1) Click the {{:genesys2:addip.jpg?nolink|}} **Add IP** button and search for **Microblaze**. +
-> +
->{{:genesys2:gsmb6.jpg?nolink&300|}} +
-> +
->Double click **Microblaze** to add it to your block design. +
-> +
->{{:genesys2:gsmb10.jpg?nolink&700|}} +
- +
->4.2) Click **Run Block Automation** to open the Block automation for the Microblaze processor. +
-> +
->Here you can choose how much memory to give your Microblaze processor. **Configure the options** to match the picture below, then click **OK**.  +
-> +
->{{:genesys2:gsmbs2.jpg?nolink&700|}} +
- +
->4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.** +
-> +
->{{:genesys2:gsmbs3.jpg?nolink&700|}} +
- +
------ +
- +
-==== 5. Adding Peripheral Components ==== +
- +
->5.1) Go into the **Boards** tab again and find the **USB UART** component. **Click and drag** this onto the block design to add the Uartlite block to your design. +
- +
->5.2) Find the **Ethernet PHY** and **drag this onto the block design** to add the Ethernet block to your design. +
-> +
->{{:genesys2:gsmbs8.jpg?nolink&500|}} +
- +
->5.3) Click the {{:genesys2:addip.jpg?nolink|}} **Add IP** button and search for **Timer**. Double click **AXI Timer** to add it to your block design. +
-> +
->{{:genesys2:gsmbs16.jpg?nolink&300|}} +
- +
->5.4) Click **Run Block Automation** in the green banner. Then click **OK** on the screen that pops up. +
-> +
->{{:genesys2:gsmbs9.jpg?nolink&500|}} +
-> +
->This will create a new Ethernet DMA IP block as well as a clock wizard. +
- +
->5.5) Find the clock wizard //axi_ethernet_0_refclk// and connect **clk_in1** to the **ui_clk** output on the //mig_7series_0// block. +
-> +
->{{:genesys2:gsmbs10.jpg?nolink&700|}} +
- +
->5.6) Click **Run Connection Automation** in the green banner. Check the **All Automation** checkbox and click **OK**. +
-> +
->{{:genesys2:gsmbs11.jpg?nolink&500|}} +
-> +
->You might get a warning about obsolete automations. Just **Run Connection Automation** again on all automations. This will create one AXI Interconnect for the DDR Memory and another for peripheral components. +
- +
------ +
- +
-====6. Connecting the Interrupts ==== +
- +
->6.1) Find the **Concat** block and double click it to open its settings. +
-> +
->{{:genesys2:gsmbs14.jpg?nolink&500|}} +
- +
->6.2) Change the **Number of Ports** to **5**. Click **OK**. +
-> +
->{{:genesys2:gsmbs15.jpg?nolink&500|}} +
- +
->6.3) The Concat block takes interrupt inputs and sends them to the Microblaze controller. +
-> +
->{{:nexys:nexysvideo:concat.jpg?nolink&300|}} +
-> +
->Route the following connections to the inputs of the //Concat// block; order does not matter: +
->   - **interrupt** on the //AXI Timer// block. +
->   - **mm2s_introut** and **s2mm_introut** on the //axi_ethernet_0_dma// block. +
->   - **mac_irq** and **interrupt** on the //axi_ethernet_0// block. +
- +
-====7. Validating Design and making an HDL Wrapper ==== +
- +
->7.1) Click the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** button to rearrange your block design. +
-> +
->{{:genesys2:gsmbs13.jpg?nolink&700|}} +
- +
->7.2) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors.  +
- +
->7.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the **Sources** tab and find your block design. +
-> +
->{{:genesys2:gsmb16.jpg?nolink&500|}} +
- +
- +
->7.4) Right click on your block design and click **Create HDL Wrapper**. **Let Vivado manage wrapper and auto-update** and click **OK**. +
-> +
->{{:genesys2:gsmb17.jpg?nolink&500|}} +
-> +
->This will create a top module in VHDL and will allow you to generate a bitstream. +
- +
------ +
- +
-====8. Generating Bit File ==== +
- +
->8.1) In the top toolbar in Vivado, click {{:genesys2:generate.jpg?nolink|}} **Generate Bitstream**. This can also be found in the //Flow Navigator// panel on the left, under //Program and Debug//. +
->If you haven't already saved your design, you will get a prompt to save the block design.  +
- +
->8.2) The bit file generation will begin. The tool will run //Synthesis// and //Implementation//. After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.  +
-> +
->This process can take anywhere from **5 to 60 minutes** depending on your computer. +
- +
->8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**.  +
- +
------ +
- +
-====9. Exporting Hardware Design to SDK ==== +
- +
->9.1) On the main toolbar, click **File** and select **Export Hardware**. Check the box to **Include Bitstream** and click **OK**. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.  +
-> +
->{{:genesys2:gsmb18.jpg?nolink|}} +
-> +
->A new file directory will be created under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace.  +
- +
->9.2) On the main toolbar, click **File** and then **Launch SDK**. Leave both of the dropdown menus as their default //Local to Project// and click **OK**. This will open Xilinx SDK and import your hardware. +
-> +
->{{:genesys2:gsmb19.jpg?nolink&300|}} +
- +
------ +
- +
-====10. Inside Xilinx SDK ==== +
- +
->10.1) The HW design specification and included IP blocks are displayed in the //system.hdf// file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.  +
-> +
->From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.  +
-> +
->{{:genesys2:gsmbs17.jpg?nolink&700|}} +
- +
->10.2) Within the //Project Explorer// tab on the left, you can see your hardware platform. +
-> +
->**system** is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information. +
- +
------ +
- +
-====11. Creating New Application Project in SDK ==== +
- +
->11.1) Click the {{:genesys2:new.jpg?nolink|}} **New** dropdown arrow and select **Application Project**. +
-> +
->{{:genesys2:gsmbs18.jpg?nolink&500|}} +
-> +
->Give your project a name that has no empty spaces and click **Next**. +
- +
->11.2) Select **lwIP Echo Server** from the list of templates and click **OK**. +
-> +
->{{:genesys2:gsmbs19.jpg?nolink&500|}} +
- +
-You will see two new folders in the **Project Explorer** panel.  +
-  * **echo_server** which contains all the binaries, .C and .H (Header) files +
-  * **echo_server_bsp** which is the board support folder  +
- +
-**echo_server** is our main working source folder. This also contains an important file shown here which is the "lscript.ld". This is a Xilinx auto generated linker script file. Double click on this file to open. +
- +
->11.3) Back in the **Project Explorer**, double click and open **system.mss** under the **echo_server_bsp** folder. Click **Modify this BSP's Settings**. +
-> +
->{{:genesys2:gsmbs20.jpg?nolink&600|}} +
- +
->11.4) Click **lwip141** then find **temac_adapter_options** and click the arrow. Find **phy_link_speed** and change the Value to **CONFIG_LINKSPEED100**. If your router supports Gigabit transfers, change this value to **CONFIG_LINKSPEED1000**. Click **OK**. +
-> +
->{{:genesys2:gsmbs21.jpg?nolink&600|}} +
- +
------ +
- +
-====12. Programming FPGA with Bit File ==== +
- +
->12.1) Make sure that the Genesys2 is turned on and connected to the host PC via both the **JTAG** USB port //and// the **UART** USB port. +
-> +
->On the top toolbar, click the {{:genesys2:programfpga.jpg?nolink|}} **Program FPGA** button. +
- +
->12.2) Click **Program** to program your FPGA with your hardware design. +
-> +
->{{:genesys2:gsmb24.jpg?nolink&500|}} +
- +
------ +
- +
-====13. Setting up UART Terminal==== +
- +
->13.1) Open up a Serial Terminal application (Tera Term). Connect to the Genesys2 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block. +
-> +
->{{:genesys2:gsmb25.jpg?nolink&500|}} +
- +
------ +
- +
-====14. Program the Microblaze Processor==== +
- +
->14.1) Make sure you have your Genesys2 plugged into a router before beginning. +
- +
->14.2) Back in SDK, select your **echo_server** project and click the {{:genesys2:run.jpg?nolink|}} **Run As...** button. Select **Launch on Hardware (System Debugger)** and click **OK**. +
-> +
->{{:genesys2:gsmbs22.jpg?nolink&300|}} +
- +
->14.3) Your program will run and you should see the IP information inside of your Serial Terminal. +
-> +
->{{:genesys2:gsmbs7.jpg?nolink&600|}} +
- +
->14.4) Connect to the echo server by opening another terminal and connecting to the **Board IP on port 7**. +
-> +
->{{:genesys2:gsmbs23.jpg?nolink&500|}} +
- +
->14.5) Test your echo server by typing something into the terminal. Depending on your settings, you might not see the characters until you press **Enter**. When you do, the message will be sent to the Echo Server, and will be echoed back onto your Terminal! +
-> +
->{{:genesys2:gsmbs24.jpg?nolink&600|}} +
- +
------+