Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
learn:programmable-logic:tutorials:vivado-hierarchical-blocks:start [2019/09/12 22:13] – Arthur Brown | learn:programmable-logic:tutorials:vivado-hierarchical-blocks:start [2022/09/12 19:41] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey | ||
---|---|---|---|
Line 1: | Line 1: | ||
====== Adding a Hierarchical Block to a Vivado IPI Design ====== | ====== Adding a Hierarchical Block to a Vivado IPI Design ====== | ||
- | ==== Inventory ==== | + | In Vivado, a // |
+ | |||
+ | ===== Inventory | ||
* A Digilent FPGA development board. | * A Digilent FPGA development board. | ||
* A computer with Vivado installed. | * A computer with Vivado installed. | ||
- | * //Following | + | * //See the [[: |
- | * //This guide was tested in Vivado 2019.2, other versions of Vivado may still work, but support is not guaranteed.// | + | |
* Familiarity with Vivado IP Integrator and a base block design to work from. | * Familiarity with Vivado IP Integrator and a base block design to work from. | ||
- | * //Following the [[: | + | * //Following the [[: |
- | ==== Guide ==== | + | ===== Guide ===== |
+ | ==== Setting Up Dependencies | ||
+ | Check if vivado-library is already included in the Vivado project, if it is not, then it should be downloaded: | ||
+ | |||
+ | {{https:// | ||
+ | |||
+ | Those familiar with git may want to clone the hierarchies rather than download a ZIP. The dropdown below contains brief instructions. | ||
+ | |||
+ | --> Using git to clone the hierarchies # | ||
+ | < | ||
+ | cd (somewhere memorable) | ||
+ | git clone https:// | ||
+ | </ | ||
+ | |||
+ | Otherwise (if vivado-library is included in the project), use git tools to check out the branch: | ||
+ | |||
+ | **Warning!** //If IP from the library are already included in the project, checking out a different branch may cause changes to them. Be careful!// | ||
+ | |||
+ | Note that the " | ||
+ | |||
+ | < | ||
+ | cd (path)/ | ||
+ | git checkout hierarchies | ||
+ | </ | ||
+ | <-- | ||
+ | |||
+ | ---- | ||
+ | ==== Adding a Hierarchical Block to a Hardware Design ==== | ||
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
=== 1. === | === 1. === | ||
+ | Launch Vivado, then open the Vivado Project the hierarchical block is to be used in, and open the project' | ||
- | Download the [[https://github.com/Digilent/vivado-hierarchies/ | + | **Note**: //The design must contain a processor and a peripheral that can be used for stdout. In the case of Microblaze, a UART IP must be connected to the board' |
+ | |||
+ | Completing the [[:vivado:getting-started-with-ipi: | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
+ | |||
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
=== 2. === | === 2. === | ||
+ | In Vivado' | ||
- | Launch Vivado. | + | When the script is finished running, the block design will contain a // |
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
+ | |||
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
=== 3. === | === 3. === | ||
- | + | Check the README.txt file, which can be found in the hierarchical block' | |
- | Create or open the Vivado Project you wish to use the Hierarchy | + | - Connect all of the hierarchical block' |
+ | - Connect any interrupts the Hierarchy may have to the appropriate interrupt controller: an AXI Interrupt Controller IP (for Microblaze designs), the Zynq Processing System' | ||
+ | - Connect any additional clocks to clocks generated by a Memory Interface Generator or a Clocking Wizard (for Microblaze designs), or a Zynq Processing System (for Zynq designs). | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
+ | |||
=== 4. === | === 4. === | ||
+ | The next step, constraining the Hierarchy' | ||
- | Create or open the project's Block Design. | + | - If a board was selected when creating |
+ | - If a part was selected instead of a board, or the Board Flow cannot be used for whatever reason, the **Manual Constraint Flow** should be used instead. | ||
---- | ---- | ||
- | === 5. === | + | == 4.1 - Creating an External Pmod Port == |
+ | Open the dropdown for the chosen Workflow, below, and follow the instructions. | ||
- | In Vivado' | + | **Note**: //This step is only required for Pmod hierarchical blocks. Zmod hierarchical scripts automatically create their external ports. For the purposes |
- | When the script is finished running, | + | --> Board Flow # |
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
+ | Go to Vivado' | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | <-- | ||
- | ---- | + | --> Manual Constraint Flow # |
- | === 6. === | + | <WRAP GROUP> <WRAP COLUMN HALF> |
- | + | Select the Pmod_out port, then right click on it and select **Make External**. Select | |
- | Make sure your design has a processor, and a peripheral that can be used for stdout. In the case of Microblaze, a UART IP must be connected to the board' | + | </ |
+ | {{ : | ||
+ | </ | ||
+ | <-- | ||
---- | ---- | ||
- | === 7. === | + | == 4.2 - Validating the Design and Creating a Wrapper File == |
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
+ | Regardless of the chosen workflow, validate the block design by clicking the Validate button ( {{: | ||
+ | Then create an HDL wrapper file, if one doesn' | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | == 4.3 - Constraining the Design | ||
+ | This step works a little differently depending on whether the peripheral targeted by the hierarchical block is a [[zmod: | ||
- | Check the README.txt file, found in your Pmod's folder in this repo, to find additional | + | --> Pmod# |
- | - Connect all of the Hierarchy' | + | <WRAP GROUP> <WRAP COLUMN HALF> |
- | - Connect any interrupts the Hierarchy may have to the appropriate interrupt controller, an AXI INTC IP (for Microblaze designs), the Zynq Processing System' | + | If the **Board Flow** was chosen, open the README.txt file in the hierarchical block's folder in vivado-library-hierarchies |
- | - Connect any additional clocks to clocks generated by a Memory Interface Generator or a Clocking Wizard (for Microblaze designs), or a Zynq Processing System (for Zynq designs). | + | |
- | ---- | + | When the Hierarchy was created, a constraint file, named " |
- | === 8. === | + | |
- | The next step, constraining | + | Constraints required for the **Board Flow** are left uncommented by default. |
- | If you selected a board while creating your project, you can use the *Board Flow* for this step: | + | If the **Manual Constraint |
- | --> Board Flow # | + | The text " |
- | - Go to Vivado' | + | Two types of manually entered values |
- | - Make sure to validate your block design, save it, and create an HDL wrapper file. | + | |
- | - Check the README.txt file in your Pmod's folder for additional instructions to determine whether any additional constraints | + | |
+ | Port Names: \\ | ||
+ | These %%FIXME%%s come after the text " | ||
+ | |||
+ | Location Constraints: | ||
+ | These %%FIXME%%s come after the text " | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
<-- | <-- | ||
- | If you selected a part instead of a board, or otherwise do not wish to use the *Board Flow*, you will need to create a port to connect to the Hierarchy' | ||
- | --> | + | --> |
+ | |||
+ | <WRAP GROUP> <WRAP COLUMN HALF> | ||
+ | When create_hier.tcl is run for a Zmod Hierarchical Block, a constraint file is imported which contains template constraints for each external port created by the script. The constraint file is named after the hierarchical block created by the script, followed by the name of the particular Zmod, for example: " | ||
+ | |||
+ | At time of writing, each Zmod Hierarchical Block provides template constraints for each of the Eclypse Z7's Zmod Ports. By default, the Zmod ADC is connected to the Eclypse Z7's Zmod Port A, and the Zmod DAC is connected to Zmod Port B. To connect to a different port, the user need only comment out the section of the xdc corresponding to the default port, and uncomment the section corresponding to the chosen port. | ||
- | - Select the Pmod\_out port, then right click on it and select *Make External*. Select | + | For other boards, the user must replace |
- | - Validate your design, and save it. If your block design doesn' | + | </ |
- | - When the Hierarchy was created, a constraint file, named " | + | {{: |
- | - The text " | + | </ |
- | - Find the correct port names for your Pmod interface by reviewing the port map of the top module near the top of the HDL wrapper file. Enter these port names into the corresponding place in the constraint file (after get\_ports, near the end of each line). | + | |
- | - Download the master XDC file for your board. Master XDC files for Digilent boards | + | |
<-- | <-- | ||
---- | ---- | ||
- | === 9. === | ||
- | Generate | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 5. === | ||
+ | Click **Generate | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 10. === | + | ==== Baremetal Software |
+ | <WRAP round center important 660px> | ||
+ | Zmod Hierarchical Blocks are supported in software by the Zmod Library. If using a Zmod, see the [[zmod: | ||
+ | </ | ||
- | Export | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 1. === | ||
+ | Export | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 11. === | ||
- | Launch SDK. | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 2. === | ||
+ | Launch | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 12. === | ||
- | Create a new Application Project | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 3. === | ||
+ | Create a new application project | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 13. === | ||
- | Copy all of the files from your Pmod' | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 4. === | ||
+ | Copy all of the files from the selected hierarchical block' | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 14. === | ||
- | Build All. | + | <WRAP GROUP> <WRAP COLUMN HALF> |
+ | === 5. === | ||
+ | Make sure that the development board' | ||
+ | |||
+ | Connect the SDK Terminal to the port associated with the board. The **green button** in the Serial Terminal pane is used to launch the //Connect to a serial port// dialog. By default, the baud rate is 115200 for Zynq, and 9600 for Microblaze (when using the AXI Uartlite IP). If desired, other terminals, such as Tera Term or PuTTY, may be used instead. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 15. === | ||
- | Plug in your board. | ||
- | ---- | + | <WRAP GROUP> <WRAP COLUMN HALF> |
- | === 16. === | + | === 6. === |
+ | Program the FPGA by selecting **Xilinx -> Program FPGA** from the top menu bar in Xilinx SDK. | ||
- | Xilinx | + | Once the FPGA is programmed, run the application project by right-clicking on the application project and selecting **Run -> Run on Hardware (System Debugger)**. |
+ | |||
+ | Messages printed by the demo application can be seen in the serial terminal. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
---- | ---- | ||
- | === 17. === | + | ===== Next Steps ===== |
+ | Now that the hierarchical block' | ||
- | Run the application project. | + | The SDK sources provided with the hierarchical blocks are set up such that they can be easily included in any design using that block. The subfolder below sdk_sources contains all necessary drivers for the block. |
+ | |||
+ | For more reference materials and guides on the Digilent products being used, navigate to their resource centers, here on the [[start: | ||
+ | |||
+ | For technical support, please visit the [[https:// | ||
- | ---- | ||
{{tag> | {{tag> |