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Genesys MIG Tutorial
This page was made to help step through the Genesys MIG wizard and to get an example project running.
Things you will need…
- ISE 14.7 installed on your computer
- Genesys Board from Digilent
- Power adapter for Genesys
- USB to micro USB cable
- Adept 2.0 from Digilent (Or IMPACT included with ISE 14.7)
Step One: Create a New Project
Open ISE 14.7 and click new project. You don't need to add any files and the device is XC5VLX50T and the package is FF1136. These settings can be seen below.
Step Two: The MIG Wizard
Click new source → IP → MIG. This will open up the MIG (Memory Interface Generator) wizard. Verify that the correct fpga shows up and click next.
On this page you will want to select Create Design. By default this is selected click next.
Pin Compatible FPGAs
This page is for creating a MIG that will also be compatible with different FPGAs. Since this is just an example design, we can leave all of these options blank and click next.
Memory Selection
The Genesys has a DDR2 SDRAM. Select this option in the drop down menu.
Controller Options
The DDR2 chip we are working with is a Micron MT4HTF3264HY-667D3. Select SODIMMs under Memory type and MT4HTF3264HY-667 under Memory Part. Data width should be 64. The page should look like this before clicking next.
Memory Options
On this page, the RTT (nominal) - ODT should be changed to 50 ohms(11). The rest of the options should be the default but it should look like the picture below.
FPGA Options
The only thing to make sure of is to select a single ended clock.
Extended FPGA Options
The correct options will be the defaults. Double check with the picture below and click next.
Reserve Pins
No pins need to be reserved and the Fixed Pin Out bubble needs to be selected to move forward. Verify with the picture then click next.
Pin Selection
To make this easier, I will include a UCF to read into this page. The UCF should be placed at project_name/ipcore_dir
Once the .ucf is in the correct position, click ReadUCF. This will populate the grid.* Now we can move to the next step.
*Note: Some pins may not be what the master UCF or the schematic claim them to be. Specifically ddr2_we# will not be correct. We will deal with this in a later step.
Summary, Memory Model, PCB Information, and Design Rules
There is some important information in these pages but for this example, we can skip to the end. Accept the license agreement then click generate. Our MIG will now generate!
Step Four: Generate example project
Open up Design suite 64 bit Command Prompt which is included in ISE 14.7 webpack.
Once open, change the directory to project_name\ipcore_dir\MIG_name\example_design\par
Run create_ise.bat
