Genesys MIG Tutorial

This page was made to help step through the Genesys MIG wizard and to get an example project running.

Things you will need…

- ISE 14.7 installed on your computer

- Genesys Board from Digilent

- Power adapter for Genesys

- USB to micro USB cable

- Adept 2.0 from Digilent (Or IMPACT included with ISE 14.7)

Open ISE 14.7 and click new project. You don't need to add any files and the device is XC5VLX50T and the package is FF1136. These settings can be seen below.

Click new source → IP → MIG. This will open up the MIG (Memory Interface Generator) wizard. Verify that the correct fpga shows up and click next.

On this page you will want to select Create Design. By default this is selected click next.

This page is for creating a MIG that will also be compatible with different FPGAs. Since this is just an example design, we can leave all of these options blank and click next.

The Genesys has a DDR2 SDRAM. Select this option in the drop down menu.

The DDR2 chip we are working with is a Micron MT4HTF3264HY-667D3. Select SODIMMs under Memory type and MT4HTF3264HY-667 under Memory Part. Data width should be 64. The page should look like this before clicking next.

On this page, the RTT (nominal) - ODT should be changed to 50 ohms(11). The rest of the options should be the default but it should look like the picture below.

The only thing to make sure of is to select a single ended clock.

The correct options will be the defaults. Double check with the picture below and click next.

No pins need to be reserved and the Fixed Pin Out bubble needs to be selected to move forward. Verify with the picture then click next.

To make this easier, I will include a UCF to read into this page. The UCF should be placed at project_name/ipcore_dir

Here is the UCF file

Once the .ucf is in the correct position, click ReadUCF. This will populate the grid.* Now we can move to the next step.

*Note: Some pins may not be what the master UCF or the schematic claim them to be. Specifically ddr2_we# will not be correct. We will deal with this in a later step.

There is some important information in these pages but for this example, we can skip to the end. Accept the license agreement then click generate. Our MIG will now generate!

For this step we will be correcting the missed placement of ddr_we#. The first thing we need to do is open up mig.prj located at project_name/ipcore_dir/MIG_name/user_design

Once in this file, change the pin location of ddr2_we# to K29. This is the correct pin for the we pin. Save the file.

Do the same thing for the mig.prj located at project_name/ipcore_dir/MIG_name/example_design

Here is the edited user_design mig.prj file

mig.zip

Open up Design suite 64 bit Command Prompt which is included in ISE 14.7 webpack.

Once open, change the directory to project_name\ipcore_dir\MIG_name\example_design\par

Run create_ise.bat

After this completes, open up test.ise located at project_name\ipcore_dir\MIG_name\example_design\par with ISE 14.7.

The MIG now requires a 266.667 Mhz clk, a 133.333 Mhz clk, a 266.667 MHz clk phase shifted by 90 degrees, and a 200 MHz clk. In order to supply the clocks we need to the MIG, a PLL to DCM is needed. Open up the IP core catalog and select PLL to DCM. In the setup, make sure the device is correct then click ok.

The next screen select CLKOUTDCM1 in the drop down menu then click next.

On this screen, CLKIN1 should be a 200 MHz Differential source. The multiple value should be set to 4 and the divide, 1. Make sure the options match the picture below. 200 * (4/3) = 266.667. In the next window we will divide by 3. Click next.

On this screen set the divide value to be 3 and verify the output clock is 266.667 MHz then click next.

ON the next screen enable the CLK90, CLKDV, and the CLKFX pins. Type 266.667 MHz into the input clock frequency. Divide by value should be 2. Compare with the picture below then click next

For the next screen we want to use all Global buffers. Click next.

On the next screen select Use M and D values. Set them to 3 and 4 respectively to regenerate a 200 MHz clk. Compare with the picture then click next.

Then click finish to complete the wizard.

CLK0_OUT → clk0

CLKDV_OUT → clkdiv0

CLKFX_OUT → clk200

CLK90_OUT → clk90

Using these wizards and the example project, here is the working project on the Genesys board. LED1 is tied to Error and should not illuminate. LED 0 should illuminate. The bit file will be found under Genesys_MIG\ipcore_dir\mem\example_design\par. Digilent's Adept software can be used to program the Genesys.

genesys_mig.zip