Differences

This shows you the differences between two versions of the page.

Link to this comparison view

dsdb:rm [2016/05/03 13:57] – [Table] Hegbeli Ciprian Mariandsdb:rm [2023/02/09 12:53] (current) – external edit 127.0.0.1
Line 1: Line 1:
- +======= DSDB Reference Manual =======
-FIXME -- Remaining TODO before First Draft submission: +
-  - Review that all references to ELVIS, MXP, and other NI products is consistent and correct +
-  - Complete "Overview" opening paragraph with additional marketing language +
-  - Write final "Overview" paragraph to highlight compatibility with existing NI software/ecosystems +
-  - Homogenize formatting of link style and references to other sections +
-  - Cleanup last sentence of section 1.1 +
-  - Consider moving power supplies section to the end or toning down some of the advanced power engineering content. +
-  - Complete MXP Section +
-  - Write Touchscreen section +
-  - Go through and fix table/figure numbering and references when content is finalized. +
- +
----- +
-====== Overview ======+
  
 {{ :dsdb:dsdb-obl-600.png?nolink&400|}} {{ :dsdb:dsdb-obl-600.png?nolink&400|}}
  
-The Digital Systems Design Board (DSDB) is an Elvis Add-On Board featuring a Zynq 7020 All-Programmable SoC (AP SoC). FIXME //-- Add additional text that introduces target audience, applications and key features//+The Digital Systems Design Board (DSDB) is an NI ELVIS Add-On Board featuring a Zynq 7020 All-Programmable SoC (AP SoC) that was designed by Digilent for National Instruments. When paired with the NI ELVIS platform, it becomes an ideal lab installation for classes centered around digital and analog circuits. The DSDB also has the ability to be used as a standalone Zynq development platform, independent of NI ELVIS.
  
 The DSDB includes the following features: The DSDB includes the following features:
Line 39: Line 26:
     * USB-JTAG Programming Circuitry     * USB-JTAG Programming Circuitry
     * Current and Voltage monitoring on expansion connectors     * Current and Voltage monitoring on expansion connectors
-    * Powered from the Elvis connector or 5V barrel jack input+    * Powered from the NI ELVIS connector or 5V barrel jack input
   * **System Connectivity**    * **System Connectivity** 
     * 16-bit VGA output     * 16-bit VGA output
     * Dual-role (Source/Sink) HDMI port     * Dual-role (Source/Sink) HDMI port
-    * Elvis Top Board connector+    * NI ELVIS Add-On connector
     * 24-bit Audio Codec with Headphone, Line out, Line in, and Mic Jacks     * 24-bit Audio Codec with Headphone, Line out, Line in, and Mic Jacks
     * 10/100/1000 Mbps Ethernet     * 10/100/1000 Mbps Ethernet
Line 58: Line 45:
   * **Expansion Connectors**   * **Expansion Connectors**
     * MXP Connector     * MXP Connector
-    * Breadboard with analog I/O from ELVIS and digital I/O from Zynq+    * Breadboard with analog I/O from NI ELVIS and digital I/O from Zynq
     * Two Pmod connectors with 8 FPGA I/O each     * Two Pmod connectors with 8 FPGA I/O each
     * One Pmod connector with 8 Processor I/O     * One Pmod connector with 8 Processor I/O
Line 64: Line 51:
 The DSDB is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE/EDK toolset. These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive design flow. They can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. The DSDB is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE/EDK toolset. These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive design flow. They can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs.
  
-FIXME --// Add text describing compatibility with NI software solutions (LabVIEW, etc.). Depending on prioritized relevance, consider swapping with Vivado paragraph above//+{{ :dsdb:dsdb-walk-around.jpg |}}
  
 ---- ----
  
-====== 1 Power Supplies ======+===== 1 Power Supplies =====
  
-The DSDB is powered from the Elvis platform or an external power supply connected to J17 (when used as a standalone platform). Connector J17 is placed in a way in which it doesn't allow the connection of an external supply when the board is plugged into the Elvis platform. This was done to prevent the user from incorrectly attaching an external supply while the ELVIS is powering the DSDB.+The DSDB is powered from the NI ELVIS platform or an external power supply connected to J17 (when used as a standalone platform). Connector J17 is placed in a way in which it doesn't allow the connection of an external supply when the board is plugged into the NI ELVIS platform. This was done to prevent the user from incorrectly attaching an external supply while the NI ELVIS is powering the DSDB.
  
-The Elvis platform can deliver maximum 2A of current on the 5V output according to the specifications. This should provide enough power for a typical use case. A typical application represents a Zynq configuration that uses all on-board peripherals, 0.2A load on each of the two user supplies (5V and 3.3V), mouse connected to the USB HID port (J9), and analog outputs in the MXP connector(J4) left floating. If more features are intended to be used, for example drawing more power from the user supplies, a power demanding FPGA configuration, or connecting a USB device that needs more than 100mA, the DSDB board should be used as standalone with an external power supply.+The NI ELVIS platform can deliver maximum 2A of current on the 5V output according to the specifications. This should provide enough power for a typical use case. A typical application represents a Zynq configuration that uses all on-board peripherals, 0.2A load on each of the two user supplies (5V and 3.3V), mouse connected to the USB HID port (J9), and analog outputs in the MXP connector(J4) left floating. If more features are intended to be used, for example drawing more power from the user supplies, a power demanding FPGA configuration, or connecting a USB device that needs more than 100mA, the DSDB board should be used as standalone with an external power supply.
  
 When used as a standalone platform an external power supply (such as a wall wart) should be used by plugging into the power jack (J17).  The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.6VDC to 5.5VDC and at least 2A of current (i.e., at least 12.5W of power) for typical use cases and 4A (20W of power) for power demanding applications. Suitable supplies can be purchased from the Digilent website or through catalog vendors like DigiKey. Power supply voltages outside the above specified range will prevent the board from powering up, while voltages above 18V will cause permanent damage. When used as a standalone platform an external power supply (such as a wall wart) should be used by plugging into the power jack (J17).  The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.6VDC to 5.5VDC and at least 2A of current (i.e., at least 12.5W of power) for typical use cases and 4A (20W of power) for power demanding applications. Suitable supplies can be purchased from the Digilent website or through catalog vendors like DigiKey. Power supply voltages outside the above specified range will prevent the board from powering up, while voltages above 18V will cause permanent damage.
  
-All on-board power supplies are enabled or disabled by the power switch SW9. The power indicator LED (LD14) is on when all the supply rails reach their nominal voltage. An overview of the power circuit is shown in Fig.FIXME+All on-board power supplies are enabled or disabled by the power switch SW9. The power indicator LED (LD14) is on when all the supply rails reach their nominal voltage. An overview of the power circuit is shown in Fig.2
  
 {{ :dsdb:dsdb_pwruser.png |}} {{ :dsdb:dsdb_pwruser.png |}}
  
-//Figure FIXME. Power circuit overview//+//Figure 2. Power circuit overview//
  
-Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input. Table FIXME provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).+Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input. Table 1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).
  
 | **Supply**  | **Circuits**                                                                                      | **Device**       | **Current (max/typical)**  | | **Supply**  | **Circuits**                                                                                      | **Device**       | **Current (max/typical)**  |
Line 101: Line 88:
 | 3.3V        | User Voltage                                                                                      | IC49: TPS2553    | 0.3A/0 to 0.3A             | | 3.3V        | User Voltage                                                                                      | IC49: TPS2553    | 0.3A/0 to 0.3A             |
  
-//Table FIXME. DSDB power supplies.//+//Table 1. DSDB power supplies.//
  
 The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW9) will enable the 5.125V (IC53) rail, which enables the 1V digital supply rail, which in turn enables the supply rails 1.8V, 3.3V and 1.5V. The 1.25V reference, 1.8V analog supply and 10V, -5V charge pumps ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC55) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply, lighting up the power LED (LD14), enabling user supplies (IC46, IC49) and power supply for user IO buffers (IC19) and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq. The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch (SW9) will enable the 5.125V (IC53) rail, which enables the 1V digital supply rail, which in turn enables the supply rails 1.8V, 3.3V and 1.5V. The 1.25V reference, 1.8V analog supply and 10V, -5V charge pumps ramp together with the 3.3V rail. Once all the channels of the ADP5052 (IC55) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply, lighting up the power LED (LD14), enabling user supplies (IC46, IC49) and power supply for user IO buffers (IC19) and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.
Line 110: Line 97:
 ==== 1.1 Input Power Monitoring ==== ==== 1.1 Input Power Monitoring ====
  
-The DSDB includes a power monitoring switch TPS25940 ([[http://www.ti.com/lit/ds/slvscf3/slvscf3.pdf]]) placed on the 5V input power rail. This circuit provides input over and undervoltage protection, fast response shortcircuit protection and slew rate controlled startup to limit inrush current. In case the input supply voltage is outside the operating range of 4.6V to 5.5V, or if the current consumption exceeds 4.4A the TPS25940 will turn off the board power. +The DSDB includes a power monitoring switch TPS25940 ([[http://www.ti.com/lit/ds/slvscf3/slvscf3.pdf|datasheet]]) placed on the 5V input power rail. This circuit provides input over and undervoltage protection, fast response shortcircuit protection and slew rate controlled startup to limit inrush current. In case the input supply voltage is outside the operating range of 4.6V to 5.5V, or if the current consumption exceeds 4.4A the TPS25940 will turn off the board power. 
 ==== 1.2 User Power Supplies ==== ==== 1.2 User Power Supplies ====
  
Line 138: Line 125:
  
  
-//Table FIXME. Analog Input pinout.//+//Table 2. Analog Input pinout.//
  
 The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs. The XADC core is controlled and accessed from the PL via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.” It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the Zynq Technical Reference Manual. The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs. The XADC core is controlled and accessed from the PL via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.” It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the Zynq Technical Reference Manual.
Line 146: Line 133:
 $$V_{USER 5V/3.3V} = \frac {N_{XADC}}{65536} * V_{REF} * \frac {1}{DIV} = \frac {N_{XADC}}{65536} * 6 $$ $$V_{USER 5V/3.3V} = \frac {N_{XADC}}{65536} * V_{REF} * \frac {1}{DIV} = \frac {N_{XADC}}{65536} * 6 $$
  
-The current information is collected across 0.1Ohm sense resistors (R431, R445) placed in front of the circuits that generate the user voltages (IC46, IC49). Since both these circuits are linear devices the input current matches the current on the output. The voltage across the sense resistor is fed into a current sense amplifier with a gain of 50, INA216A2 [[http://www.ti.com/lit/ds/symlink/ina216.pdf]], and divided by 5 before it is connected to the XADC inputs. Equation below shows how to compute current from the XADC number:+The current information is collected across 0.1Ohm sense resistors (R431, R445) placed in front of the circuits that generate the user voltages (IC46, IC49). Since both these circuits are linear devices the input current matches the current on the output. The voltage across the sense resistor is fed into a current sense amplifier with a gain of 50, INA216A2 ([[http://www.ti.com/lit/ds/symlink/ina216.pdf|datasheet]]), and divided by 5 before it is connected to the XADC inputs. Equation below shows how to compute current from the XADC number:
  
 $$I_{USER 5V/3.3V} = \frac {N_{XADC}}{65536} * V_{REF} * \frac {1}{GAIN} * \frac {1}{DIV} * \frac {1}{R_{SENSE}} = \frac {N_{XADC}}{65536} * 1 $$ $$I_{USER 5V/3.3V} = \frac {N_{XADC}}{65536} * V_{REF} * \frac {1}{GAIN} * \frac {1}{DIV} * \frac {1}{R_{SENSE}} = \frac {N_{XADC}}{65536} * 1 $$
 ---- ----
-====== 2 Zynq AP SoC Architecture ======+===== 2 Zynq AP SoC Architecture =====
  
  The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic (PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the device found on this board.   The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic (PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the device found on this board. 
Line 156: Line 143:
 {{ :zybo:zyng1.png?500 |}} {{ :zybo:zyng1.png?500 |}}
  
-//Figure FIXME. Zynq AP SoC architecture//+//Figure 3. Zynq AP SoC architecture//
  
 The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly by the processor or via the JTAG port. The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly by the processor or via the JTAG port.
Line 163: Line 150:
  
 There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the Zynq Technical Reference Manual, available at www.xilinx.com.  There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the Zynq Technical Reference Manual, available at www.xilinx.com. 
-Figure FIXME depicts the external components connected to the MIO pins of the DSDB. +Table 3 depicts the external components connected to the MIO pins of the DSDB. 
  
 | **MIO 500 3.3 V**  | **Peripherals**  | **Peripherals**  | **Peripherals**  | | **MIO 500 3.3 V**  | **Peripherals**  | **Peripherals**  | **Peripherals**  |
Line 216: Line 203:
  
  
-//Table FIXME. MIO Pinout//+//Table 3. MIO Pinout//
  
 ---- ----
  
-====== 3 Zynq Configuration ======+===== 3 Zynq Configuration =====
  
 Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application.  Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application. 
Line 269: Line 256:
 ---- ----
  
-====== 4 Connecting to Elvis ======+===== 4 Connecting to NI ELVIS =====
 The DSDB is fully integrated with the [[http://sine.ni.com/nips/cds/view/p/lang/en/nid/205425 | NI ELVIS]] platform, which features 12 of the most commonly used instruments in the laboratory including an oscilloscope, digital multimeter, function generator, variable power supplies, digital reader/writer, two- and three-wire current-voltage analyzers, and a Bode analyzer. Integration with the NI ELVIS platform gives students the ability to build comprehensive test benches and analog mixed-signal circuits that can be designed and tested in one platform. The DSDB is also capable of running stand-alone when the advanced functionality of the NI ELVIS is not required. The DSDB is fully integrated with the [[http://sine.ni.com/nips/cds/view/p/lang/en/nid/205425 | NI ELVIS]] platform, which features 12 of the most commonly used instruments in the laboratory including an oscilloscope, digital multimeter, function generator, variable power supplies, digital reader/writer, two- and three-wire current-voltage analyzers, and a Bode analyzer. Integration with the NI ELVIS platform gives students the ability to build comprehensive test benches and analog mixed-signal circuits that can be designed and tested in one platform. The DSDB is also capable of running stand-alone when the advanced functionality of the NI ELVIS is not required.
  
-The signals from the Elvis edge connector are routed to the Power breadboard header, the Elvis Analog breadboard header, and the programmable logic of the Zynq. The connections are described in Tables FIXME and FIXME below. ELVIS pins not listed in the tables below are not connected to any device on the DSDB. Note that +5V from this connector is also used to power the entire board. The GND pins of the ELVIS connector, the ground plane of the DSDB, and the pins labeled GND on the breadboard headers are all connected. For further information on the functionality of the pins on the ELVIS connector please refer to the NI ELVIS documentation. +The signals from the NI ELVIS edge connector are routed to the Power breadboard header, the NI ELVIS Analog breadboard header, and the programmable logic of the Zynq. The connections are described in Tables 4 and 5 below. NI ELVIS pins not listed in the tables below are not connected to any device on the DSDB. Note that +5V from this connector is also used to power the entire board. The GND pins of the NI ELVIS connector, the ground plane of the DSDB, and the pins labeled GND on the breadboard headers are all connected. For further information on the functionality of the pins on the NI ELVIS connector please refer to the NI ELVIS documentation. 
  
-^ Elvis Pin  ^ Breadboard Header  ^ Breadboard Pin  ^+^ NI ELVIS Pin  ^ Breadboard Header  ^ Breadboard Pin  ^
 | +15V       | Power              | +15V            | | +15V       | Power              | +15V            |
 | -15V       | Power              | -15V            | | -15V       | Power              | -15V            |
Line 291: Line 278:
 | AI2-       | Analog             | AI2-            | | AI2-       | Analog             | AI2-            |
  
-Table FIXME. Elvis Breadboard Connections+Table 4. NI ELVIS Breadboard Connections
  
-^ ELVIS Pin  ^ Zynq Pin  ^+^ NI ELVIS Pin  ^ Zynq Pin  ^
 | DIO0       | Y20       | | DIO0       | Y20       |
 | DIO1       | AA16      | | DIO1       | AA16      |
Line 314: Line 301:
 | PFI12      | R21       | | PFI12      | R21       |
  
-Table FIXME. Elvis Zynq Connections+Table 5. NI ELVIS Zynq Connections
  
 ---- ----
    
-====== 5 SPI Flash ======+===== 5 SPI Flash =====
  
 The DSDB features a Quad-SPI serial flash device, the Spansion S25FL128S. The Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem (bitstream).  The DSDB features a Quad-SPI serial flash device, the Spansion S25FL128S. The Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem (bitstream). 
Line 332: Line 319:
 ---- ----
  
-====== 6 DDR3 Memory ======+===== 6 DDR3 Memory =====
  
 The DSDB includes two Micron MT41J128M16JT-125 or MT41K128M16JT-125 DDR3 memory components creating a single rank, 32-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Xilinx Zynq TRM (ug585).  The DSDB includes two Micron MT41J128M16JT-125 or MT41K128M16JT-125 DDR3 memory components creating a single rank, 32-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Xilinx Zynq TRM (ug585). 
Line 356: Line 343:
 ---- ----
  
-====== 7 USB UART Bridge (Serial Port) ======+===== 7 USB UART Bridge (Serial Port) =====
  
  
Line 367: Line 354:
 ---- ----
  
-====== 8 microSD Slot ======+===== 8 microSD Slot =====
  
-The DSDB provides a microSD slot (J15) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table FIXME. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the Zynq TRM, SDIO host mode is the only mode supported.+The DSDB provides a microSD slot (J15) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 6. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the Zynq TRM, SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
Line 380: Line 367:
 | **SD_CD**        | Card Detect      | MIO47         | 9                | | **SD_CD**        | Card Detect      | MIO47         | 9                |
  
-//Table 4. microSD pinout//+//Table 6. microSD pinout//
  
 The SD slot is a powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually 2-port SDIO port expander, but only its level shifter function is used. Mapping out the correct pins and configuring the interface is handled by the DSDB board definition file. The SD slot is a powered from 3.3V, but is connected through MIO Bank 1/501 (1.8V). Therefore, a TI TXS02612 level shifter performs this translation. The TXS02612 is actually 2-port SDIO port expander, but only its level shifter function is used. Mapping out the correct pins and configuring the interface is handled by the DSDB board definition file.
Line 390: Line 377:
 ---- ----
  
-====== 9 USB HID Host ======+===== 9 USB HID Host =====
  
 The Auxiliary Function microcontroller (Microchip® PIC24FJ128) provides USB HID host capability. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J9 labeled "USB HID". The PIC24 then emulates a PS/2 device towards the FPGA over two PS/2 ports. Port 0 is always keyboard, while port 1 is always mouse. Hub support is not currently available, so only a single mouse or keyboard can be used at any time. The Auxiliary Function microcontroller (Microchip® PIC24FJ128) provides USB HID host capability. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J9 labeled "USB HID". The PIC24 then emulates a PS/2 device towards the FPGA over two PS/2 ports. Port 0 is always keyboard, while port 1 is always mouse. Hub support is not currently available, so only a single mouse or keyboard can be used at any time.
Line 398: Line 385:
 | PS/2 Mouse      | Data   | PS2_DATA1      | Y21       | | PS/2 Mouse      | Data   | PS2_DATA1      | Y21       |
 | :::             | Clock  | PS2_CLK1       | U11       | | :::             | Clock  | PS2_CLK1       | U11       |
 +//Table 7. USB HID pinout//
  
  
Line 405: Line 392:
 ===== 9.1 HID Controller ===== ===== 9.1 HID Controller =====
  
-The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the DSDB, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in Fig. 8.+The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the DSDB, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in Fig. 4.
  
 {{ :common:ps2:timing_diagram.png |Figure 8. PS/2 device-to-host timing diagram.}} {{ :common:ps2:timing_diagram.png |Figure 8. PS/2 device-to-host timing diagram.}}
  
-//Figure 8. PS/2 device-to-host timing diagram.//+//Figure 4. PS/2 device-to-host timing diagram.//
  
 The clock and data signals are only driven when data transfers occur; otherwise, they are held in the idle state at logic '1'. This requires that when the PS/2 signals are used in a design, internal pull-ups must be enabled in the FPGA on the data and clock pins. The clock signal is normally driven by the device, but may be held low by the host in special cases. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface. The clock and data signals are only driven when data transfers occur; otherwise, they are held in the idle state at logic '1'. This requires that when the PS/2 signals are used in a design, internal pull-ups must be enabled in the FPGA on the data and clock pins. The clock signal is normally driven by the device, but may be held low by the host in special cases. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.
Line 420: Line 407:
 PS/2 uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports). PS/2 uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports).
  
-PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in Fig. 9.+PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in Fig. 5.
  
-{{ :nexys-video:keyboard_scan_codes.png |Figure 9. Keyboard scan codes.}}+{{ :nexys-video:keyboard_scan_codes.png |Figure 5. Keyboard scan codes.}}
  
-//Figure 9. Keyboard scan codes.//+//Figure 5. Keyboard scan codes.//
  
  
-A host device can also send data to the keyboard. Table 7 shows a list of some common commands a host might send.+A host device can also send data to the keyboard. Table 8 shows a list of some common commands a host might send.
  
  
Line 438: Line 425:
  
  
-//Table 7. Keyboard commands//+//Table 8. Keyboard commands//
  
 The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a "clear to send" signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a '0' start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit, and terminated with a '1' stop bit. The keyboard generates 11 clock transitions (at 20 to 30 KHz) when the data is sent, and data is valid on the falling edge of the clock. The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a "clear to send" signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a '0' start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit, and terminated with a '1' stop bit. The keyboard generates 11 clock transitions (at 20 to 30 KHz) when the data is sent, and data is valid on the falling edge of the clock.
Line 449: Line 436:
 The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a '1' indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement: the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a '1' means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a '1' indicates the button is being pressed). The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a '1' indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement: the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a '1' means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a '1' indicates the button is being pressed).
  
-{{ :common:ps2:mouse_data_format.png |Figure 10. Mouse data format.}} +{{ :common:ps2:mouse_data_format.png |Figure 9. Mouse data format.}} 
-//Figure 10. Mouse data format.//+//Figure 6. Mouse data format.//
  
-The microcontroller also supports Microsoft® IntelliMouse®-type extensions for reporting back a third axis representing the mouse wheel, as shown in Table 8. +The microcontroller also supports Microsoft® IntelliMouse®-type extensions for reporting back a third axis representing the mouse wheel, as shown in Table 9. 
  
 ^ Command  ^ Action                                                                                                                                                                                                                                                       ^ ^ Command  ^ Action                                                                                                                                                                                                                                                       ^
Line 463: Line 450:
  
  
-//Table 8. Microsoft Intellimouse type extensions, commands and actions//+//Table 9. Microsoft Intellimouse type extensions, commands and actions//
  
  
 ---- ----
  
-====== 10 Ethernet ======+===== 10 Ethernet =====
  
 The DSDB uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via Reduced gigabit media-independent interface (RGMII) for data and MDIO for management. The auxiliary interrupt (ETH_INT_B) and reset (ETH_RST_B) signals connect to PL pins to be accessed via EMIO.  The DSDB uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via Reduced gigabit media-independent interface (RGMII) for data and MDIO for management. The auxiliary interrupt (ETH_INT_B) and reset (ETH_RST_B) signals connect to PL pins to be accessed via EMIO. 
Line 474: Line 461:
 After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured. After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured.
  
-Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD12) and valid link state (LD11). Table FIXME shows the default behavior.+Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD12) and valid link state (LD11). Table 10 shows the default behavior.
  
 |  **Function**  |  **Designator**  |  **State**                |  **Description**                            | |  **Function**  |  **Designator**  |  **State**                |  **Description**                            |
Line 482: Line 469:
  
  
-//Table FIXME. Ethernet status LEDs.//+//Table 10. Ethernet status LEDs.//
  
 The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the PS preset, part of the board definition files. The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the PS preset, part of the board definition files.
Line 502: Line 489:
 ---- ----
  
-====== 11 OLED ======+===== 11 OLED =====
  
-A Univision Technology Inc. UG-2832HSWEG04 is loaded on the DSDB. It is a white monochrome, 128 x 32, 0.91" organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards the Zynq programmable logic is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up sequencing. The signals are summarized in Table FIXME.+A Univision Technology Inc. UG-2832HSWEG04 is loaded on the DSDB. It is a white monochrome, 128 x 32, 0.91" organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards the Zynq programmable logic is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up sequencing. The signals are summarized in Table 11.
  
 ^ Signal  ^ Description                             ^ Polarity     ^ FPGA pin  ^ ^ Signal  ^ Description                             ^ Polarity     ^ FPGA pin  ^
Line 516: Line 503:
  
  
-Table FIXME. OLED signal description.+Table 11. OLED signal description.
  
 The serial interface is synchronous to SCLK and must conform to the timing specifications below. In most cases, a 10 MHz SCLK and data sent on the falling edge should work. The serial interface is synchronous to SCLK and must conform to the timing specifications below. In most cases, a 10 MHz SCLK and data sent on the falling edge should work.
Line 522: Line 509:
 {{ :nexys-video:serial-interface_timing_diagram.png |}} {{ :nexys-video:serial-interface_timing_diagram.png |}}
  
-//Figure FIXME. Serial interface timing diagram.//+//Figure 7. Serial interface timing diagram.//
  
 {{ :nexys-video:oled_serial_interface.png |}} {{ :nexys-video:oled_serial_interface.png |}}
  
-//Figure FIXME. OLED serial interface bit ordering.//+//Figure 8. OLED serial interface bit ordering.//
  
 ^ Symbol  ^ Parameter               ^ Min  ^ Typ.  ^ Max  ^ Unit  ^ ^ Symbol  ^ Parameter               ^ Min  ^ Typ.  ^ Max  ^ Unit  ^
Line 541: Line 528:
 | t<sub>F</sub>      | Fall Time               | -    | -     | 40   | ns    | | t<sub>F</sub>      | Fall Time               | -    | -     | 40   | ns    |
  
-//Table FIXME. Timing diagram symbols and parameters.//+//Table 12. Timing diagram symbols and parameters.//
  
 Start-up sequence: Start-up sequence:
   - Power up VDD by pulling OLED_VDD low. Wait 1ms.   - Power up VDD by pulling OLED_VDD low. Wait 1ms.
   - Pulse RES# low for at least 3us.   - Pulse RES# low for at least 3us.
-  - Send initialization/configuration commands (see Table FIXME).+  - Send initialization/configuration commands (see Table 13).
   - Power up VBAT by pulling OLED_VBAT low. Wait 100ms for voltage to stabilize.   - Power up VBAT by pulling OLED_VBAT low. Wait 100ms for voltage to stabilize.
   - Clear screen by writing zero to the display buffer.   - Clear screen by writing zero to the display buffer.
Line 562: Line 549:
  
  
-//Table FIXME. OLED configuration commands//+//Table 13. OLED configuration commands//
  
 After start-up, writing to the display is done by sending data bytes over the serial interface (D/C# high). Each data bit corresponds to a pixel with the addressing mode, inversion, and scan direction settings determining exactly which. After start-up, writing to the display is done by sending data bytes over the serial interface (D/C# high). Each data bit corresponds to a pixel with the addressing mode, inversion, and scan direction settings determining exactly which.
Line 569: Line 556:
 ---- ----
  
-====== 12 VGA Port ======+===== 12 VGA Port =====
  
 The DSDB board uses 18 programmable logic pins to create an analog VGA output port. This translates to 16-bit color depth and two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync). The DSDB board uses 18 programmable logic pins to create an analog VGA output port. This translates to 16-bit color depth and two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync).
-The digital-to-analog conversion is done using a simple R-2R resistor ladder¹. The ladder works in conjunction with the 75-ohm termination resistance of the VGA display to create 32 and 64 analog signal levels red, blue, and green VGA signals. This circuit, shown in Fig. 8, produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). With 5 bits each for red and blue and 6 bits for green, 65,536 (32×32×64) different colors can be displayed, one for each unique 16-bit pattern.+The digital-to-analog conversion is done using a simple R-2R resistor ladder ([[http://en.wikipedia.org/wiki/Resistor_ladder|Wikipedia]]). The ladder works in conjunction with the 75-ohm termination resistance of the VGA display to create 32 and 64 analog signal levels red, blue, and green VGA signals. This circuit, shown in Fig. 8, produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). With 5 bits each for red and blue and 6 bits for green, 65,536 (32×32×64) different colors can be displayed, one for each unique 16-bit pattern.
  
-A video controller circuit must be created in programmable logic to drive the sync and color signals with the correct timing in order to produce a working display system +A video controller circuit must be created in programmable logic to drive the sync and color signals with the correct timing in order to produce a working display system.
- +
-¹http://en.wikipedia.org/wiki/Resistor_ladder+
  
 ==== 12.1 VGA System Timing ==== ==== 12.1 VGA System Timing ====
Line 584: Line 569:
 NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website. NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website.
  
-CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Fig. FIXME).+CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Fig. 9).
  
 {{ :common:vga:cathode_display.png?400 |}} {{ :common:vga:cathode_display.png?400 |}}
  
-//Figure FIXME. Color CRT display.//+//Figure 9. Color CRT display.//
  
 Electron beams emanate from “electron guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.” The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow. Electron beams emanate from “electron guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.” The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow.
  
-Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom, as shown in Fig. FIXME. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point.+Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom, as shown in Fig. 10. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point.
  
 Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution.  Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution. 
Line 601: Line 586:
 {{ :common:vga:sync_signals.png?400 |}} {{ :common:vga:sync_signals.png?400 |}}
  
-//Figure FIXME. VGA horizontal synchronization.//+//Figure 10. VGA horizontal synchronization.//
  
 Video data typically comes from a video refresh memory; with one or more bytes assigned to each pixel location (the DSDB uses 16 bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel. Video data typically comes from a video refresh memory; with one or more bytes assigned to each pixel location (the DSDB uses 16 bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel.
  
-A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Fig. FIXME can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays.+A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Fig. 11 can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays.
  
 {{ :common:vga:timing.png?400 |}} {{ :common:vga:timing.png?400 |}}
  
-//Figure FIXME. Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh//+//Figure 11. Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh//
  
-A VGA controller circuit, such as the one diagramed in Fig. FIXME, decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and you can use this counter to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.+A VGA controller circuit, such as the one diagramed in Fig. 12, decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and you can use this counter to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.
  
 {{ :common:vga:sync_generator.png?500 |}} {{ :common:vga:sync_generator.png?500 |}}
  
-//Figure FIXME. VGA display controller block diagram.//+//Figure 12. VGA display controller block diagram.//
  
 ---- ----
  
-====== 13 HDMI Source/Sink Port ======+===== 13 HDMI Source/Sink Port =====
  
 An input and output-capable HDMI Port connects to the programmable logic pins. Over this connector an HDMI or DVI-compatible video stream can be driven in or out of the DSDB. Encoding or decoding the HDMI/DVI video stream needs to be implemented in logic, as well as auxiliary functions, like DDC or CEC. Depending on the actual design, it can take the Source role driving a monitor/TV display, or behave as a Sink accepting a video stream from any HDMI/DVI Source, like a laptop or smartphone. An input and output-capable HDMI Port connects to the programmable logic pins. Over this connector an HDMI or DVI-compatible video stream can be driven in or out of the DSDB. Encoding or decoding the HDMI/DVI video stream needs to be implemented in logic, as well as auxiliary functions, like DDC or CEC. Depending on the actual design, it can take the Source role driving a monitor/TV display, or behave as a Sink accepting a video stream from any HDMI/DVI Source, like a laptop or smartphone.
  
-On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and Sink. These signals are summarized Table FIXME.+On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and Sink. These signals are summarized Table 14.
  
-|  **Signal**  |  **Role**  |  **Description**                                             |  **Direction (Zynq POW)**  |  **How to control**  | +|  **Signal**  |  **Role**  |  **Description**                                             |  **Direction (Zynq POW)**          |  **How to control**  | 
-|  **HPD**     | Source     | Hot-plug detect; signals the presence of a Sink to a Source  | Input                      | HDMI_OUT_EN = 1      | +|  **HPD**     | Source     | Hot-plug detect; signals the presence of a Sink to a Source  | Input (requires internal pull-up)  | HDMI_OUT_EN = 1      | 
-| :::          | Sink       | :::                                                          | Output                     | HDMI_OUT_EN = 0      | +| :::          | Sink       | :::                                                          | Output                             | HDMI_OUT_EN = 0      | 
-|  **5V0**     | Source     | Auxiliary power for Sink                                     | Output                     | HDMI_OUT_EN = 1      | +|  **5V0**     | Source     | Auxiliary power for Sink                                     | Output                             | HDMI_OUT_EN = 1      | 
-| :::          | Sink       | :::                                                          | Input                      | HDMI_OUT_EN = 0      |+| :::          | Sink       | :::                                                          | Input                              | HDMI_OUT_EN = 0      |
  
-//Table FIXME. HDMI signal direction in Source and Sink roles.+//Table 14. HDMI signal direction in Source and Sink roles.
 // //
  
Line 645: Line 630:
 ---- ----
  
-====== 14 Touchscreen Display ======+===== 14 Touchscreen Display =====
  
 The DSDB has a TFT-LCD with a capacitive touch panel mounted on the LCD. The LCD is a 5" diagonal, 800 x 480 RGB display with a 24-bit color depth. The touch panel size has been scaled to the LCD so that every point read from the touch panel can be converted to a RGB pixel on the TFT-LCD. Although the LCD and touch panel come as an assembly, they have independent controllers and are driven separately.  The DSDB has a TFT-LCD with a capacitive touch panel mounted on the LCD. The LCD is a 5" diagonal, 800 x 480 RGB display with a 24-bit color depth. The touch panel size has been scaled to the LCD so that every point read from the touch panel can be converted to a RGB pixel on the TFT-LCD. Although the LCD and touch panel come as an assembly, they have independent controllers and are driven separately. 
Line 651: Line 636:
 ==== 14.1 LCD Display ==== ==== 14.1 LCD Display ====
  
-The LCD has a ILI6122 timing controller mounted on it which interfaces to the TFT display. The user has access only to certain pins of the controller which enable him to send data to the LCD. In order to access the controller pins the LCD uses a strip connector with the following pin-out.+The LCD has a ILI6122 timing controller mounted on it which interfaces to the TFT display. The user has access only to certain pins of the controller, specifically those which are used to send data to the LCD. In order to access the controller pins the LCD uses a strip connector with the following pin-out.
 ^ Pin      ^ Signal           ^ Description                                                 ^ ^ Pin      ^ Signal           ^ Description                                                 ^
 | 1        | BCK_LED_K        | Back-light LED cathode. Connected to the FP6745 LED driver  | | 1        | BCK_LED_K        | Back-light LED cathode. Connected to the FP6745 LED driver  |
Line 669: Line 654:
 | 36       | GND              | Ground                                                      | | 36       | GND              | Ground                                                      |
 | 37 - 40  | NC               | Not connected                                               | | 37 - 40  | NC               | Not connected                                               |
-//Table FIXME LCD control signals//+//Table 15. LCD control signals//
  
-In order to facilitate the dimming of the back-light on the LCD, the FP6745 LED driver has been used. The user has direct access to the enable pin of the LED-driver; by driving this pin with a PWM signal the user will obtain a variety of back-light intensities dependent on the duty cycle of the PWM signal. When driving the back-light whit PWM it is highly recommended to choose a PWM frequency above 20 KHz, because this circuit may interfere with the Audio circuit. +In order to facilitate the dimming of the back-light on the LCD, the FP6745 LED driver has been used. The user has direct access to the enable pin of the LED-driver; by driving this pin with a PWM signal the user will obtain a variety of back-light intensities dependent on the duty cycle of the PWM signal. When driving the back-light with PWM it is highly recommended to choose a PWM frequency above 20 KHz, because this circuit may interfere with the Audio circuit. 
-Before starting to use the LCD the DSIP pin must be set to logic high. This pin is an enable pin which allows the user to turn off the display without interrupting the timing and data flow. When sending data to the display the following timing specifications must be respected:+Before starting to use the LCD the DISP pin must be set to logic high. This pin is an enable pin which allows the user to turn off the display without interrupting the timing and data flow. When sending data to the display the following timing specifications must be respected:
  
 **Horizontal** **Horizontal**
  
 {{ :dsdb:dsdb_tft_hs.png |}} {{ :dsdb:dsdb_tft_hs.png |}}
-//Fig. FIXME Horizontal timing//+//Figure 13. Horizontal timing//
  
 ^  Horizontal Input Timing                                                    ||||||| ^  Horizontal Input Timing                                                    |||||||
Line 690: Line 675:
 | Horizontal back porch            || thbp     | 46      | 46     | 46     | CLKIN  | | Horizontal back porch            || thbp     | 46      | 46     | 46     | CLKIN  |
 | Horizontal front porch           || thfp     | 16      | 210    | 354    | CLKIN  | | Horizontal front porch           || thfp     | 16      | 210    | 354    | CLKIN  |
-//Table FIXME LCD control signals//+//Table 16. Horizontal timing//
  
 **Vertical** **Vertical**
  
 {{ :dsdb:dsdb_tft_vs.png |}} {{ :dsdb:dsdb_tft_vs.png |}}
-//Fig. FIXME Horizontal timing//+//Figure 14. Vertical timing//
  
 ^  Vertical Input Timing                                             |||||| ^  Vertical Input Timing                                             ||||||
Line 705: Line 690:
 | Vertical back porch     | tvbp     | 23      | 23     | 23     | HS     | | Vertical back porch     | tvbp     | 23      | 23     | 23     | HS     |
 | Vertical front porch    | tvfp     | 7       | 22     | 147    | HS     | | Vertical front porch    | tvfp     | 7       | 22     | 147    | HS     |
-//Table FIXME Vertical timing//+//Table 17. Vertical timing//
  
 These timing constraints are similar to the VGA functionality presented in a previous chapter, but the timing specifications have to be strictly respected in order to ensure the correct functionality of the device. These timing constraints are similar to the VGA functionality presented in a previous chapter, but the timing specifications have to be strictly respected in order to ensure the correct functionality of the device.
Line 719: Line 704:
 | 5    | TP_RES  | Reset signal, has a pull-up resistor  | | 5    | TP_RES  | Reset signal, has a pull-up resistor  |
 | 6    | GND     | Ground                                | | 6    | GND     | Ground                                |
-//Table FIXME Touch panel pin-out //+//Table 18. Touch panel pin-out //
  
-The addressing mode of the I2C is is on 7 bit, with the slave address being 0111000 in binary and the maximum frequency at which the controller can operate is 400 KHz. Additionally to the  I2C protocol there are two other signals provided by the controller, the REST and the INT signal. In order to reset the touch panel controller the RESET pin has to be driven low for at least 1 ms. The INT signal is an I/O signal which will go low while the panel is being touched, when the FT5x16 is in hibernation the same INT signal must be used in order to wake the controller up. When using the INT signal in order to wake the controller, the low pulse generate for the wake-up sequence must be driven low for 0.5 to 1 ms, the reason for this short period is that the INT port will act as an interrupt output port after the wake-up.+The addressing mode of the I2C is 7 bit, with the slave address being 0111000 in binary and the maximum frequency at which the controller can operate is 400 KHz. In addition to the I2C bus there are two other signals provided by the controller, the RESET and the INT signal. In order to reset the touch panel controller the RESET pin has to be driven low for at least 1 ms. The INT signal is an I/O signal which will go low while the panel is being touched. Also, when the FT5x16 is in hibernation the same INT signal must be used in order to wake the controller up. When using the INT signal in order to wake the controller, the low pulse generate for the wake-up sequence must be driven low for 0.5 to 1 ms. The reason for this short period is that the INT port will act as an interrupt output port after the wake-up.
  
 The following registers can be used in order to obtain a minimal functionality of the touch panel: The following registers can be used in order to obtain a minimal functionality of the touch panel:
  
-FIXME//**The registers have to be updated**// +This is the device mode register, which is configured to determine the current mode of the chip.(Read/Write)
- +
-//This is the device mode register, which is configured to determine the current mode of the chip.//+
 ^ Address  ^ Bit Address  ^ Register Name      ^ Description                              ^ ^ Address  ^ Bit Address  ^ Register Name      ^ Description                              ^
 |  00h     | 6:4          | Device Mode [2:0]  | 000b Normal operating Mode               | |  00h     | 6:4          | Device Mode [2:0]  | 000b Normal operating Mode               |
Line 733: Line 716:
 | :::      | :::          | :::                | 100b FACTORY MODE0 (Reserved)            | | :::      | :::          | :::                | 100b FACTORY MODE0 (Reserved)            |
 | :::      | :::          | :::                | 110b FACTORY MODE1 (Reserved)            | | :::      | :::          | :::                | 110b FACTORY MODE1 (Reserved)            |
----+//Table 19. Device Mode Register//
  
-//This register describes MSB of the X coordinate of the nth touch point and the corresponding event flag.//+This register describes MSB of the X coordinate of the nth touch point and the corresponding event flag.(Read only)
 ^ Address       ^ Bit Address  ^ Register Name            ^ Description                        ^ ^ Address       ^ Bit Address  ^ Register Name            ^ Description                        ^
 |  03h ~ 1Bh    | 7:6          | Event Flag               | 00b: Press Down                    | |  03h ~ 1Bh    | 7:6          | Event Flag               | 00b: Press Down                    |
Line 743: Line 726:
 | :::           | 5:4          |                          | Reserved                           | | :::           | 5:4          |                          | Reserved                           |
 | :::           | 3:0          | Touch X Position [11:8]  | MSB of Touch X Position in pixels  | | :::           | 3:0          | Touch X Position [11:8]  | MSB of Touch X Position in pixels  |
 +//Table 20. X MSB Register//
  
---- +This register describes LSB of the X coordinate of the nth touch point.(Read only)
- +
-//This register describes LSB of the X coordinate of the nth touch point.//+
 ^ Address     ^ Bit Address  ^ Register Name           ^ Description                            ^ ^ Address     ^ Bit Address  ^ Register Name           ^ Description                            ^
 |  04h ~ 1Ch  | 7:0          | Touch X Position [7:0]  | LSB of the Touch X Position in pixels  | |  04h ~ 1Ch  | 7:0          | Touch X Position [7:0]  | LSB of the Touch X Position in pixels  |
 +//Table 21. X LSB Register//
  
---- +This register describes MSB of the Y coordinate of the nth touch point and corresponding touch ID.(Read only)
- +
-//This register describes MSB of the Y coordinate of the nth touch point and corresponding touch ID.//+
 ^ Address     ^ Bit Address  ^ Register Name            ^ Description                             ^ ^ Address     ^ Bit Address  ^ Register Name            ^ Description                             ^
 |  05h ~ 1Dh  | 7:4          | Touch ID[3:0]            | Touch ID of Touch Point (0-4 is valid)  | |  05h ~ 1Dh  | 7:4          | Touch ID[3:0]            | Touch ID of Touch Point (0-4 is valid)  |
 | :::         | 3:0          | Touch Y Position [11:8]  | MSB of Touch Y Position in pixels       | | :::         | 3:0          | Touch Y Position [11:8]  | MSB of Touch Y Position in pixels       |
 +//Table 22. Y MSB Register//
  
---- +This register describes LSB of the Y coordinate of the nth touch point.(Read only)
- +
-//This register describes LSB of the Y coordinate of the nth touch point.//+
 ^ Address     ^ Bit Address  ^ Register Name           ^ Description                            ^ ^ Address     ^ Bit Address  ^ Register Name           ^ Description                            ^
-|  04h ~ 1Ch  | 7:0          | Touch X Position [7:0]  | LSB of the Touch X Position in pixels  |+|  06h ~ 1Eh  | 7:0          | Touch Y Position [7:0]  | LSB of the Touch Y Position in pixels  | 
 +//Table 23. Y LSB Register//
  
 ---- ----
-====== 15 Clock Sources ======+===== 15 Clock Sources =====
  
 The DSDB provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps).  The DSDB provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). 
Line 776: Line 757:
 ---- ----
  
-====== 16 Basic I/O ======+===== 16 Basic I/O =====
  
 The DSDB includes a four-digit seven segment display, eight slide switches, four push buttons, and eight individual LEDs connected to the Zynq PL. There is also one LED connected directly to the PS via MIO pin 7. The push buttons and slide switches are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push button or slide switch was inadvertently defined as an output). The push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position. The DSDB includes a four-digit seven segment display, eight slide switches, four push buttons, and eight individual LEDs connected to the Zynq PL. There is also one LED connected directly to the PS via MIO pin 7. The push buttons and slide switches are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push button or slide switch was inadvertently defined as an output). The push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position.
Line 786: Line 767:
 ==== 16.1 Seven-Segment Display ==== ==== 16.1 Seven-Segment Display ====
  
-The DSDB contains a four-digit common anode seven-segment LED display. Each of the four digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure FIXME. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.+The DSDB contains a four-digit common anode seven-segment LED display. Each of the four digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure 15. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.
  
-{{ nexys4-ddr:n4s.png?600 |}} +{{ :basys3-_seven_segment_display.png?600 |}} 
-FIXME -- fix figure label by removing from image and placing in text+//Figure 15. Digit Illumination Patterns//
  
-The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Fig FIXME. The common anode signals are available as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the four “D” cathodes from the four digits are grouped together into a single circuit node called “CD.”  These seven cathode signals are available as inputs to the 4-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted. +The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Fig 16. The common anode signals are available as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the four “D” cathodes from the four digits are grouped together into a single circuit node called “CD.”  These seven cathode signals are available as inputs to the 4-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted. 
  
 To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the DSDB uses transistors to drive enough current into the common anode point, the anode enables are inverted. Therefore, both the AN0..3 and the CA..G/DP signals are driven low when active. To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the DSDB uses transistors to drive enough current into the common anode point, the anode enables are inverted. Therefore, both the AN0..3 and the CA..G/DP signals are driven low when active.
  
 {{ :basys3-_seven_segment_display_driving.png?500 |}} {{ :basys3-_seven_segment_display_driving.png?500 |}}
-FIXME -- Fix figure label+//Figure 16. Common Anode Circuit Node//
  
 A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect. Each digit is illuminated just one-fourth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed in the display. A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect. Each digit is illuminated just one-fourth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed in the display.
  
-For each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/4 of the refresh cycle, or 4ms. The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show “71” in the first two digits. An example timing diagram for a four-digit controller is shown in Figure FIXME.+For each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/4 of the refresh cycle, or 4ms. The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show “71” in the first two digits. An example timing diagram for a four-digit controller is shown in Figure 17.
  
-{{ nexys4-ddr:n4u.png?400 |}} +{{ :basys3-seven_segment_timing_diagram.png?400 |}} 
-FIXME -- fix figure label+//Figure 17. Four digit scanning display controller timing diagram//
 ---- ----
- +===== 17 Audio =====
-====== 17 Audio ======+
  
 An Analog Devices SSM2603 Audio Codec provides integrated digital audio processing to the Zynq programmable logic. It allows for stereo record and playback at sample rates from 8 kHz to 96 kHz. An Analog Devices SSM2603 Audio Codec provides integrated digital audio processing to the Zynq programmable logic. It allows for stereo record and playback at sample rates from 8 kHz to 96 kHz.
Line 818: Line 798:
 | **J11**          | Line In          | Stereo        | Light Blue  | | **J11**          | Line In          | Stereo        | Light Blue  |
  
-//Table FIXME. Analog audio signals//+//Table 24. Analog audio signals//
  
 The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred via the I²S protocol. Configuration is done over an I2C bus. The device address of the SSM2603 is 0011010b. All digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank. The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred via the I²S protocol. Configuration is done over an I2C bus. The device address of the SSM2603 is 0011010b. All digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank.
Line 833: Line 813:
 | **MCLK**         | Master Clock                  | Output                    | L22           | | **MCLK**         | Master Clock                  | Output                    | L22           |
  
-//Table FIXME. Digital audio signals, with the SSM2603 in default slave mode.//+//Table 25. Digital audio signals, with the SSM2603 in default slave mode.//
  
 The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For other frequencies and their respective configuration parameters, consult the SSM2603 datasheet. The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For other frequencies and their respective configuration parameters, consult the SSM2603 datasheet.
  
-The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals is specified in Table FIXME. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this mode, the codec generates the proper frequencies for these clocks. Digilent recommends that the audio codec be used in slave mode, because this tends to simplify the clocking scheme of the FPGA logic. No matter where are the clocks are generated, PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the Zynq. +The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals is specified in Table 25. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this mode, the codec generates the proper frequencies for these clocks. Digilent recommends that the audio codec be used in slave mode, because this tends to simplify the clocking scheme of the FPGA logic. No matter where are the clocks are generated, PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the Zynq. 
  
-The timing diagram of an I²S stream can be seen on Figure FIXME. Note the one-cycle delay of the data stream with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the diagram.+The timing diagram of an I²S stream can be seen on Figure 18. Note the one-cycle delay of the data stream with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the diagram.
  
 {{ :zybo:aud1.png?500 |}} {{ :zybo:aud1.png?500 |}}
  
-//Figure FIXME. I²S timing diagram.//+//Figure 18. I²S timing diagram.//
  
 The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive this signal high. It is important to note that the audio codec will not receive or transmit any audio data until the MUTE signal is driven high. The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive this signal high. It is important to note that the audio codec will not receive or transmit any audio data until the MUTE signal is driven high.
Line 851: Line 831:
 ---- ----
  
-====== 18 Reset Sources ======+===== 18 Reset Sources =====
  
  
Line 868: Line 848:
 ----- -----
  
-====== 19 User IO Protection ======+===== 19 User IO Protection =====
  
-All digital IOs that are connected to expansion connectors like Pmods, MXP, and digital breadboard provide a protection scheme to avoid destruction of the Zynq in case of accidental connections. This protection circuit includes series 33Ohm PTCs (PRG18BB330MB1RB [[http://www.murata.com/en-us/products/productdetail?partno=PRG18BB330MB1RB]]), a clamping diode to 5V and a FET Bus Switch SN74CBT3384C ([[http://www.ti.com/lit/ds/symlink/sn74cbt3384c.pdf]]), connected on the Zynq side. The 33Ohm PTC together with the diode are responsible to clamp any input voltage to 5V. Moreover the 33Ohm PTC prevents short circuits that can occur if the user accidentaly drives a signal that is supposed to be used as an input. +All digital IOs that are connected to expansion connectors like Pmods, MXP, and digital breadboard provide a protection scheme to avoid destruction of the Zynq in case of accidental connections. This protection circuit includes series 33Ohm PTCs (PRG18BB330MB1RB, [[http://www.murata.com/en-us/products/productdetail?partno=PRG18BB330MB1RB|datasheet]]), a clamping diode to 5V and a FET Bus Switch SN74CBT3384C ([[http://www.ti.com/lit/ds/symlink/sn74cbt3384c.pdf|datasheet]]), connected on the Zynq side. The 33Ohm PTC together with the diode are responsible to clamp any input voltage to 5V. Moreover the 33Ohm PTC prevents short circuits that can occur if the user accidentaly drives a signal that is supposed to be used as an input. 
  
 The SN74CBT3384C provides the possibility to connect input signal levels up to 5V, by limiting the voltage going into the Zynq pin to 3.3V. It should be noted that output signals are only compatible with 3.3V standards. Moreover this Bus Switch disconnects the user IOs from the Zynq in case the PGOOD signal is deasserted or the USER_POWER_EN signal is specifically driven low by the user. For more details on the USER_POWER_EN signal see section **1.2 User Power Supplies**. The SN74CBT3384C provides the possibility to connect input signal levels up to 5V, by limiting the voltage going into the Zynq pin to 3.3V. It should be noted that output signals are only compatible with 3.3V standards. Moreover this Bus Switch disconnects the user IOs from the Zynq in case the PGOOD signal is deasserted or the USER_POWER_EN signal is specifically driven low by the user. For more details on the USER_POWER_EN signal see section **1.2 User Power Supplies**.
Line 880: Line 860:
 ---- ----
  
-====== 20 Pmod Connectors ======+===== 20 Pmod Connectors =====
  
-Pmod connectors are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V user power supplies (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig. FIXME. The 3.3V user supply is current limited to 0.3A and it is shared between Pmods, digital breadboard and MXP connector (J4). See section **1.2 User Power Supplies** and **1.3 User Power Supplies Monitoring** for a detailed description.+Pmod connectors are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V user power supplies (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig. 19. The 3.3V user supply is current limited to 0.3A and it is shared between Pmods, digital breadboard and MXP connector (J4). See section **1.2 User Power Supplies** and **1.3 User Power Supplies Monitoring** for a detailed description.
  
-{{ :zybo:pmod1f.png?300 |}} +{{ :basys3-pmod_connector.png?300 |}} 
-FIXME -- Remove figure label from picture and correctly label in text+//Figure 19. Pmod Connecter Front View//
  
 Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information.
  
-The DSDB has three Pmod connectors, some of which behave differently than others. Each Pmod connector falls into one of two categories: standard or MIO connected. Table FIXME specifies which category each Pmod falls into, and also lists the Zynq pins they are connected to. +The DSDB has three Pmod connectors, some of which behave differently than others. Each Pmod connector falls into one of two categories: standard or MIO connected. Table 26 specifies which category each Pmod falls into, and also lists the Zynq pins they are connected to. 
  
 | Pmod JA (Standard)  | Pmod JB (Standard)  | Pmod JC (MIO)  | | Pmod JA (Standard)  | Pmod JB (Standard)  | Pmod JC (MIO)  |
Line 901: Line 881:
 | JA10: AA8           | JB10: AA4           | JC10: E6       | | JA10: AA8           | JB10: AA4           | JC10: E6       |
  
-//Table FIXME. Pmod pinout//+//Table 26. Pmod pinout//
  
 The following sections describe the differences between the Pmod types. The following sections describe the differences between the Pmod types.
Line 914: Line 894:
 ---- ----
  
-====== 21 MXP Connector ======+===== 21 MXP Connector =====
  
-The myRIO Extension Port (MXP) Connector is a standard connector interface designed by NI to provide an interoperable [[http://sine.ni.com/nips/cds/view/p/lang/en/nid/212739 | ecosystem of educational add-ons]].  The following figure shows the signals on the DSDB MXP connector.+The myRIO Extension Port (MXP) Connector is a standard connector interface designed by NI to provide an interoperable [[http://sine.ni.com/nips/cds/view/p/lang/en/nid/212739 | ecosystem of educational add-ons]]. This connector was included on the DSDB to provide the Zynq with access to these add-ons. The following figure shows the signals on the DSDB MXP connector.
  
 {{ :dsdb:mxp-pinout.png |}} {{ :dsdb:mxp-pinout.png |}}
 +//Figure 20. MXP Pins//
  
 ^ Signal Name ^ Reference ^ Direction ^ Description ^ ^ Signal Name ^ Reference ^ Direction ^ Description ^
Line 930: Line 911:
 |  UART.TX  |  DGND  |  Output  | UART transmit output. UART lines are electrically identical to DIO lines. | |  UART.TX  |  DGND  |  Output  | UART transmit output. UART lines are electrically identical to DIO lines. |
 |  DGND  |  N/A  |  N/A  | Reference for digital signals, +5 V, and +3.3 V. | |  DGND  |  N/A  |  N/A  | Reference for digital signals, +5 V, and +3.3 V. |
 +//Table 27. MXP Pin Descriptions//
 +
 +The +3V3 pin is driven by the 3V3_USER of the DSDB, and the +5V pin is driven by the 5V0_USER rail. See section **1 Power Supplies** for information on the characteristics of these power rails.
 +
 +DIO0-DIO15, UART.RX and UART.TX are connected to the programmable logic of the Zynq via protection circuitry as described in section **19 User IO Protection**.
 +
 +AO0 and AO1 are driven by a TI DAC7562SDSC 2-channel Digital to Analog converter ([[http://www.ti.com/lit/ds/symlink/dac7562.pdf|datasheet]]). AO0 is connected to channel A of the DAC and AO1 is connected to channel B. The serial interface of the DAC is connected to the programmable logic of the Zynq.
  
-FIXME -- //Confirm all signals exist on DSDB and expand on electrical specs listed below//+AI0-AI3 are connected to a TI ADS7950SBRGE 4-channel Analog to Digital Converter ([[http://www.ti.com/lit/ds/symlink/ads7950.pdf|datasheet]]). AI0 is connected to channel 0 of the ADC, AI1 is connected to channel 1, and so on. The serial interface of the ADC is connected to the programmable logic of the Zynq.
  
-  * Describe power/digital IO/Analog IO +For the Zynq pin assignments of DIO0-DIO15, UART.RX, UART.TX, the DAC serial bus and the ADC serial bus see the Master XDC available on the [[dsdb:dsdb|DSDB Digilent Resource Center]].
-  * ADC/DAC description, link to datasheets +
-  * Add information on any additional protection/power circuitry on DSDB+
  
 ---- ----
-====== 22 Breadboards ======+===== 22 Breadboards =====
  
 The DSDB board includes a large solderless prototyping area composed of 165 x 35mm breadboard and 165 x 10mm power strip, and three breadboards with signal connections that give access to on-board signals and power supplies.   The DSDB board includes a large solderless prototyping area composed of 165 x 35mm breadboard and 165 x 10mm power strip, and three breadboards with signal connections that give access to on-board signals and power supplies.  
  
 {{ :dsdb:dsdb_breadboard_labels.png |}} {{ :dsdb:dsdb_breadboard_labels.png |}}
-//Figure FIXME. Signal Breadboards with pinout//+//Figure 21. Signal Breadboards with pinout//
  
 Each of the three signal breadboards has different functions described in the following section.  Each of the three signal breadboards has different functions described in the following section. 
  
-==== 22.1 Elvis Analog Breadboard ====+==== 22.1 NI ELVIS Analog Breadboard ====
  
-This breadboard gives access to the analog capabilities of the Elvis II development system. Analog signals are routed directly from the Elvis edge connector to the breadboard. Pin markings on the breadboard match the Elvis signal naming convention. For detailed information visit the NI Elvis II Series User Manual [[http://www.ni.com/pdf/manuals/374629c.pdf]] and specifications [[http://www.ni.com/pdf/manuals/372590b.pdf]].+This breadboard gives access to the analog capabilities of the NI ELVIS development system. Analog signals are routed directly from the NI ELVIS edge connector to the breadboard. Pin markings on the breadboard match the NI ELVIS signal naming convention. For detailed information visit the NI ELVIS Series [[http://www.ni.com/pdf/manuals/374629c.pdf|User Manual]] and [[http://www.ni.com/pdf/manuals/372590b.pdf|Specifications]].
  
 ==== 22.2 FPGA Digital IO Breadboard ==== ==== 22.2 FPGA Digital IO Breadboard ====
Line 959: Line 945:
 ==== 22.3 Power Breadboard ==== ==== 22.3 Power Breadboard ====
  
-The Power Breadboard makes available to the user the power supplies generated by Elvis: the positive and negative programmable supplies, -15V and +15V. For detailed information visit the NI Elvis II Series User Manual http://www.ni.com/pdf/manuals/374629c.pdf and specifications http://www.ni.com/pdf/manuals/372590b.pdf.+The Power Breadboard makes available to the user the power supplies generated by NI ELVIS, including the positive and negative programmable supplies, -15V and +15V. For detailed information visit the NI ELVIS Series [[http://www.ni.com/pdf/manuals/374629c.pdf|User Manual]] and [[http://www.ni.com/pdf/manuals/372590b.pdf|Specifications]].
  
-Besides Elvis power supplies the Power Breadboard gives access to the 5V power input that supplies the entire board. This 5V rail can come from an external wall supply or the 5V output from Elvis, depending on the use case. For more information on powering options see section ** 1. Power Supplies **.+Besides NI ELVIS power supplies the Power Breadboard gives access to the 5V power input that supplies the entire board. This 5V rail can come from an external wall supply or the 5V output from NI ELVIS, depending on the use case. For more information on powering options see section ** 1. Power Supplies **.