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zmod:scope:reference-manual [2022/07/22 16:58] – [3.2. Calibration Memory] fix typo Arthur Brown | zmod:scope:reference-manual [2024/01/09 12:00] (current) – [Table] Laszlo Attila Kovacs | ||
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+ | ====== Zmod Scope Reference Manual ====== | ||
+ | Formerly known as the Zmod ADC. | ||
+ | |||
+ | The Digilent Zmod Scope is an open-source hardware SYZYGY™ ((The “SYZYGY™ ” mark is owned by Opal Kelly.))compatible pod containing a dual-channel ADC and the associated front end. The Zmod Scope is intended to be used with any SYZYGY™ compatible carrier board having the required capabilities. | ||
+ | |||
+ | {{Digilent Image Gallery | ||
+ | | image = {{: | ||
+ | | image = {{: | ||
+ | | image = {{: | ||
+ | }} | ||
+ | |||
+ | The Zmod Scope was designed to be a piece in a modular, HW and SW open-source ecosystem. The Zmod Scope can acquire two signals, with simultaneous sampling. Combined with a SYZYGY™ carrier, other SYZYGY™ compatible pods, Zmod Scope can be used for a variety of applications: | ||
+ | |||
+ | * There are multiple members in the Zmod Scope family: | ||
+ | * Zmod Scope 1410-40: 14-bit, 40MSPS | ||
+ | * Zmod Scope 1410-105: 14-bit, 105MSPS | ||
+ | * Zmod Scope 1410-125: 14-bit, 125MSPS | ||
+ | * Zmod Scope 1210-40: 12-bit, 40MSPS | ||
+ | * Zmod Scope 1210-125: 12-bit, 125MSPS | ||
+ | * Zmod Scope 1010-40: 10-bit, 40MSPS | ||
+ | * Zmod Scope 1010-125: 10-bit, 125MSPS | ||
+ | |||
+ | The Zmods in the family are similar, with small loading and performance differences, | ||
+ | |||
+ | |||
+ | ===== Features ===== | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Features/ | ||
+ | | ADC | AD9251BCPZ-40 | ||
+ | | Input Channels | ||
+ | | Input range - Low Range | ±1V ||||||| | ||
+ | | Input range - High Range | ±25V | ||
+ | | Resolution [bits] | ||
+ | | Absolute resolution - Low Range | 0.13mV | ||
+ | | Absolute resolution - High Range | 3.2mV | 3.2mV | 3.2mV | 12.8mV | ||
+ | | Accuracy [% of Input range] | ||
+ | | Sample rate - max [MSPS] | ||
+ | | Analog Bandwidth @ 3dB | 20 MHz | 70 MHz | 70 MHz | 20 MHz | 70 MHz | 20 MHz | 70 MHz | | ||
+ | | Analog Bandwidth @ 0.5dB | 8 MHz | 30 MHz | 30 MHz | 8 MHz | 30 MHz | 8 MHz | 30 MHz | | ||
+ | | Analog Bandwidth @ 0.1dB | 4 MHz | 20 MHz | 20 MHz | 4 MHz | 20 MHz | 4 MHz | 20 MHz | | ||
+ | | Input resistance [MΩ] | 1 MΩ/18 pF | ||
+ | ===== 1. Architectural Overview and Block Diagram ===== | ||
+ | |||
+ | This document describes the Zmod Scope' | ||
+ | |||
+ | Zmod Scope' | ||
+ | |||
+ | The **Analog Input** block is also called the **Scope**, because of similar structure and behavior to such a front end. The signals in this circuitry use a " | ||
+ | |||
+ | * The** Analog Inputs/ | ||
+ | * **Input Divider and Gain Selection**: | ||
+ | * **Buffer**: high impedance buffer | ||
+ | * **Driver**: provides appropriate signal levels and protection to the ADC. | ||
+ | * **Scope Reference**: | ||
+ | * **ADC**: the analog-to-digital converter for both scope channels. | ||
+ | * The **Power Supplies and Control** block generates all internal supply voltages. | ||
+ | * The **MCU** works as a I2C memory for two different purposes: | ||
+ | * The **DNA** includes the standard [[https:// | ||
+ | * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Zmod Scope includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data and the generated signals | ||
+ | |||
+ | In the sections that follow, schematics are not shown separately for identical blocks. | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | ---- | ||
+ | ===== 2. Scope ===== | ||
+ | |||
+ | ==== 2.1. Scope Input Divider and Gain Selection ==== | ||
+ | |||
+ | [[# | ||
+ | |||
+ | C< | ||
+ | |||
+ | The IC1 relay switches between two symmetrical R-C dividers. Each of them provide: | ||
+ | * Scope input impedance = 1MOhm || 18pF | ||
+ | * Two different attenuations for high-gain/ | ||
+ | * Controlled capacitance, | ||
+ | * Constant attenuation over a large frequency range (trimmer adjusted) | ||
+ | The maximum voltage rating for scope inputs is limited to: | ||
+ | |||
+ | $$-50V< | ||
+ | |||
+ | The DC low gain is: $$\frac {V_{SC-LG}}{V_{SCOPE-SMA}}=\frac {R_5}{R_1+R_3+R_5}=0.04\label{2}\tag{2}$$ | ||
+ | |||
+ | The High Range (at low gain): $$-25V \le V_{SCOPE-SMA} | ||
+ | |||
+ | The high gain is: $$\frac {V_{SC-HG}}{V_{SCOPE-SMA}} = \frac {R_4 + R_6}{R_2 + R_4 + R_6} = 0.96 \label{4}\tag{4}$$ | ||
+ | |||
+ | The Low Range (at high gain): $$-1V \le V_{SCOPE-SMA} \le 1V \label{5}\tag{5}$$ | ||
+ | |||
+ | The two dividers are designed to have the same equivalent impedance (both active and reactive): | ||
+ | |||
+ | $$R_{ech} = R_1 + R_3 + R_5 = R_2 + R_4 + R_6 = 1Mohm\label{6}\tag{6}$$ | ||
+ | |||
+ | Experiments shown that there are significant parasitic capacities of the layout and buffer input stage: C< | ||
+ | |||
+ | $$C_3*R_2 = (C_{PH} + C_6)*(R_4+R_6)\label{7}\tag{7}$$ | ||
+ | $$(C_{PH} + C_6) = \frac{C_3*R_2}{R_4+R_6} = 18pF\label{8}\tag{8}$$ | ||
+ | |||
+ | $$(C_4 + C_5)*(R_1 + R_3) = (C_{PL} + C_7)*R_5\label{9}\tag{9}$$ | ||
+ | $$(C_{PL} + C_7) = (C_4 + C_5)*\frac{(R_1 + R_3)}{R_5}\label{10}\tag{10}$$ | ||
+ | |||
+ | With the chosen values, the correct adjustment results in about mid-position of trimmers C< | ||
+ | |||
+ | $$C_5 = C_6 = 7pF\label{11}\tag{11}$$ | ||
+ | |||
+ | which solves the parasitic capacities as: | ||
+ | |||
+ | $$C_{PH} = 11pF\label{12}\tag{12}$$ | ||
+ | $$C_{PL} = 8.8pF\label{13}\tag{13}$$ | ||
+ | |||
+ | The Low Gain and High Gain dividers have very close equivalent capacitance, | ||
+ | |||
+ | $$C_{HGech} = \frac{C_3*R_2}{R_2+R_4+R_6} = C_{ech} = 17.28pF\label{14}\tag{14}$$ | ||
+ | $$C_{LGech} = \frac{(C_7+C_{PL})*R_5}{R_1+R_3+R_5} = 16.03p\label{15}\tag{15}$$ | ||
+ | |||
+ | Experiments show that the equivalent capacitances are even closer than the values above, about 18pF. The computing error mainly derives from trimmer position approximation. | ||
+ | |||
+ | $$C_{ech} = 18p\label{16}\tag{16}$$ | ||
+ | |||
+ | The IC2 relay shorts the C1 capacitor when DC coupling is desired. Otherwise, C1 forms a High Pass filter with the selected divider, for AC coupling, with the corner frequency: | ||
+ | |||
+ | $$f_c = \frac{1}{2*\pi*R_{ech}*(C_{ech}+C_{1})} \approx \frac{1}{2*\pi*R_{ech}*C_{1}} = 10.6Hz\label{17}\tag{17}$$ | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | IC1 and IC2 in [[# | ||
+ | The nominal coil voltage is 4.5V. | ||
+ | |||
+ | The IC16, IC17 and IC18 in [[# | ||
+ | |||
+ | * Low RDS(on) outputs | ||
+ | * Standby mode with zero current drain | ||
+ | * Small 2 × 2 DFN package | ||
+ | * Crossover Current protection | ||
+ | * Thermal Shutdown protection | ||
+ | |||
+ | Normally, all of them have both HIN and LIN inputs " | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | IC14 and IC15 in [[# | ||
+ | |||
+ | * 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic | ||
+ | * Wide supply voltage range from 1.2 V to 5.5 V | ||
+ | * CMOS low power consumption | ||
+ | * Direct interface with TTL levels | ||
+ | * Inputs accept voltages up to 5 V | ||
+ | * Complies with JEDEC standard: | ||
+ | * JESD8-7A (1.65 V to 1.95 V) | ||
+ | * JESD8-5A (2.3 V to 2.7 V) | ||
+ | * JESD8-C/ | ||
+ | * ESD protection: | ||
+ | * HBM JESD22-A114F exceeds 2000 V | ||
+ | * MM JESD22-A115-B exceeds 200 V | ||
+ | * CDM JESD22-C101E exceeds 1000 V | ||
+ | * Specified from -40 °C to +85 °C and -40 °C to +125 °C | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ==== 2.2. Scope Buffer ==== | ||
+ | |||
+ | The scope buffer stage provides very high impedance as load for the input divider. | ||
+ | |||
+ | The gain is: $$\frac {V_{BUFF}}{V_{SC-HLG}}=1\label{20}\tag{20}$$ | ||
+ | |||
+ | The actual input and output range (for nominal usage) is: | ||
+ | |||
+ | $-1V< | ||
+ | ==== 2.3. Scope Reference ==== | ||
+ | |||
+ | The scope reference stage generates the 1V reference voltage for the ADC, as well as other internal reference voltages. | ||
+ | |||
+ | $$V_{REFADC}=1V\label{23}\tag{23}$$ | ||
+ | |||
+ | |||
+ | ==== 2.4. Scope Driver ==== | ||
+ | |||
+ | The ADC driver is used for: | ||
+ | * Driving the differential inputs of the ADC (with low impedance outputs) | ||
+ | * Providing the common mode voltage for the ADC | ||
+ | * ADC protection. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ==== 2.5. Scope ADC ==== | ||
+ | |||
+ | The Zmod Scope uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC, as shown in [[# | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | The differential inputs are driven via a low-pass filter comprised of C114 together with R13, R15, R16, R17 in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by 4 to operate the ADC. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | ||
+ | |||
+ | The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V by the SYZYGY™ voltage V< | ||
+ | |||
+ | The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data. | ||
+ | ---- | ||
+ | |||
+ | ==== 2.6. Scope Signal Scaling ==== | ||
+ | |||
+ | The nominal differential ADC input voltage range is: | ||
+ | |||
+ | $$-1V< | ||
+ | |||
+ | The total scope gains (from the SMA connectors to the ADC inputs) are: | ||
+ | |||
+ | $$Low \; gain = \frac{V_{ADC\; | ||
+ | $$High \; gain = \frac{V_{ADC\; | ||
+ | |||
+ | Considering the ADC input voltage range shown in \ref{33}: | ||
+ | |||
+ | $$at \; low \; gain: -26.3V< | ||
+ | $$at \; high \; gain: -1.1V< | ||
+ | |||
+ | To cover component value tolerances and to allow software calibration, | ||
+ | |||
+ | $$at \; low \; gain: -25V< | ||
+ | $$at \; high \; gain: -1V< | ||
+ | |||
+ | With the 14-bit ADC, the absolute resolution of the scope is (see [[# | ||
+ | |||
+ | $$at \; low \; gain: \frac{52.6V}{2^{n}}\label{43}\tag{43}$$ | ||
+ | $$at \; high \; gain: \frac{2.12V}{2^{n}}n\label{44}\tag{44}$$ | ||
+ | |||
+ | For V< | ||
+ | |||
+ | $$V_{in} = \frac{N \cdot Range \cdot (1+CG)}{2^{n-1}} + CA \label{45}\tag{45}$$ | ||
+ | |||
+ | where: | ||
+ | * n = the number of bits (14 for Zmod Scope 14XX, 12 for Zmod Scope 12XX, 10 for Zmod Scope 10XX) | ||
+ | * N = the n bit, 2's complement integer number returned by the ADC | ||
+ | * V< | ||
+ | * CA = calibration Additive constant (for the appropriate channel and gain; see [[# | ||
+ | * CG = calibration Gain constant (for the appropriate channel and gain; see [[# | ||
+ | * Range = the ideal Range of the Scope input stage (approximation of the values in equation \ref{40}): | ||
+ | * 1.086 (for low range: ±1V) or | ||
+ | * 26.25 (for high range: ±25V) | ||
+ | |||
+ | ---- | ||
+ | ==== 2.7 Scope Spectral Characteristics ==== | ||
+ | |||
+ | [[# | ||
+ | The signal swept from 800kHz to 80MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were further processed to display the input stage frequency characteristics, | ||
+ | |||
+ | For Zmod Scope XXXX-100MHz and Zmod Scope XXXX-125MHz, | ||
+ | For Zmod Scope XXXX-40MHz, for both scales, the 3dB bandwidth is 20MHz+. The 0.5dB bandwidth is 8MHz and the 0.1dB bandwidth is 4MHz | ||
+ | |||
+ | The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The bandwidth @ 0.5dB, means a flatness error of a max 5.6%, while bandwidth @ 0.1dB means flatness error of a max 1.1%. | ||
+ | |||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ===== 3. MCU ===== | ||
+ | |||
+ | The [[https:// | ||
+ | |||
+ | The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as " | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | * Program Memory Type: Flash | ||
+ | * Program Memory Size (KB): 4 | ||
+ | * CPU Speed (MIPS/ | ||
+ | * SRAM Bytes: 256 | ||
+ | * Data EEPROM/HEF (bytes): 256 | ||
+ | * Digital Communication Peripherals: | ||
+ | * Capture/ | ||
+ | * Timers: 1 x 8-bit, 1 x 16-bit | ||
+ | * Number of Comparators: | ||
+ | * Temperature Range (C): -40 to 85 | ||
+ | * Operating Voltage Range (V): 1.8 to 5.5 | ||
+ | * Pin Count: 14 | ||
+ | * Low Power: Yes | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Address | ||
+ | | 0x8000 - 0x80FF | ||
+ | | 0x8100 - 0x817F | ||
+ | | 0x8180 - 0x83FF | ||
+ | ==== 3.1. SYZYGY™ DNA ==== | ||
+ | |||
+ | The Zmod Scope is compliant with [[https:// | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Contents | ||
+ | | DNA full data length | ||
+ | | DNA header length | ||
+ | | SYZYGY DNA major version | ||
+ | | SYZYGY DNA minor version | ||
+ | | Required SYZYGY DNA major version | ||
+ | | Required SYZYGY DNA minor version | ||
+ | | Maximum operating 5V load (mA) | uint16 | ||
+ | | Maximum operating 3.3V load (mA) | uint16 | ||
+ | | Maximum VIO load (mA) | uint16 | ||
+ | | Attribute flags | uint16 | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Manufacturer name length | ||
+ | | Product name length | ||
+ | | Product model / Part number length | ||
+ | | Product version / revision length | ||
+ | | Serial number length | ||
+ | | RESERVED | ||
+ | | CRC-16 (most significant byte) | uint8 | 1 | b) | 0x8026 | ||
+ | | CRC-16 (least significant byte) | uint8 | 1 | c) | 0x8027 | ||
+ | | END DATA HEADER | ||
+ | | Manufacturer name | string | ||
+ | | Product name | string | ||
+ | | Product model / Part number | ||
+ | | Product version / revision | ||
+ | | Serial number | ||
+ | | Product ID | uint32 | ||
+ | |||
+ | ^ a) ^ 13 | for Zmod Scope 1410 | | ||
+ | | ::: | 17 | for Zmod Scope 1410-105 | ||
+ | | ::: | 17 | for Zmod Scope XXXX-125 | ||
+ | | ::: | 16 | for Zmod Scope XXXX-40 | ||
+ | | b) | CRC computed over the addresses 0x8000-0x8025: | ||
+ | | c) | CRC computed over the addresses 0x8000-0x8025: | ||
+ | | d) | the subsequent address (hexadecimal) | ||
+ | | e) | Zmod Scope 1410, Zmod Scope 1410-105, Zmod Scope 1410-125, Zmod Scope 1210-125, Zmod Scope 1010-125, Zmod Scope 1410-40, Zmod Scope 1210-40, Zmod Scope 1010-40 - upon case || | ||
+ | | f) | A, B, C, etc - upon case || | ||
+ | | g) | 0x80100200 Zmod Scope 1410-105 | ||
+ | | | 0x80101200 Zmod Scope 1010-40 | ||
+ | | | 0x80102200 Zmod Scope 1210-40 | ||
+ | | | 0x80103200 Zmod Scope 1410-40 | ||
+ | | | 0x80104200 Zmod Scope 1010-125 | ||
+ | | | 0x80105200 Zmod Scope 1210-125 | ||
+ | | | 0x80106200 Zmod Scope 1410-125 | ||
+ | |||
+ | ==== 3.2. Calibration Memory ==== | ||
+ | |||
+ | The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, | ||
+ | |||
+ | * 0.1% resistors and 1% capacitors in all the critical analog signal paths | ||
+ | * Capacitive trimmers for balancing the Scope Input Divider and Gain Selection | ||
+ | * No other mechanical trimmers (as these are big, expensive, unreliable and affected by vibrations, aging, and temperature drifts) | ||
+ | * Software calibration, | ||
+ | * User software calibration, | ||
+ | |||
+ | A software calibration is performed on each device as a part of the manufacturing test. Reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod Scope device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user performing an in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible. | ||
+ | |||
+ | The Software reads the calibration parameters from the Zmod Scope MCU via the I2C bus and uses them to correct the acquired signals. | ||
+ | The structure of the calibration data is shown below: | ||
+ | |||
+ | // | ||
+ | ^ Heading 1 | ** Name ** ^ Size (Bytes) | ||
+ | | Magic ID | ||
+ | | Calibration Time | ||
+ | | Channel 1 LG Gain | CG | 4 | ||
+ | | Channel 1 LG Offset | ||
+ | | Channel 1 HG Gain | CG | 4 | ||
+ | | Channel 1 HG Offset | ||
+ | | Channel 2 LG Gain | CG | 4 | ||
+ | | Channel 2 LG Offset | ||
+ | | Channel 2 HG Gain | CG | 4 | ||
+ | | Channel 2 HG Offset | ||
+ | | Reserved Area | | ||
+ | | Log | | ||
+ | | CRC | | ||
+ | |||
+ | |||
+ | // | ||
+ | |||
+ | ^ | ||
+ | | 0x7000 - 0x707F | ||
+ | | 0x7080 - 0x70FF | ||
+ | |||
+ | At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write any other number to the magic address. | ||
+ | |||
+ | // | ||
+ | ^ Magic Number | ||
+ | | 0xD2 | ||
+ | |||
+ | |||
+ | ---- | ||
+ | |||
+ | |||
+ | ===== 4. Power Supplies and Control ===== | ||
+ | |||
+ | This block includes the internal power supplies. | ||
+ | |||
+ | The Zmod Scope gets the digital rails from the carrier board, via the SYZYGY connector: | ||
+ | |||
+ | * VCC5V0 - used for relays and analog supplies | ||
+ | * VCC3V3 - used for the MCU and analog supplies | ||
+ | * Vadj = 1.8V - used for the ADC digital rail | ||
+ | |||
+ | |||
+ | The internal analog rails sequence is: | ||
+ | |||
+ | * AVCC1V8 - ADC analog rail | ||
+ | * AVCC3V0 - ADC driver | ||
+ | * AVCC-2V5, AVCC4V5 - Scope buffer, reference voltage | ||
+ | |||
+ | |||
+ | |||
+ | ==== 4.1. AVCC1V8 ==== | ||
+ | |||
+ | The analog supply AVCC1V8 is built from VCC5V0 using IC21, an [[http:// | ||
+ | |||
+ | * Input voltage: 2.3 V to 5.5 V | ||
+ | * Peak efficiency: 95% | ||
+ | * 3 MHz fixed frequency operation | ||
+ | * Typical quiescent current: 24 μA | ||
+ | * Very small solution size | ||
+ | * 6-lead, 1 mm × 1.5 mm WLCSP package | ||
+ | * Fast load and line transient response | ||
+ | * 100% duty cycle low dropout mode | ||
+ | * Internal synchronous rectifier, compensation, | ||
+ | * Current overload and thermal shutdown protections | ||
+ | * Ultra-low shutdown current: 0.2 μA (typical) | ||
+ | * Forced PWM and automatic PWM/PSM modes | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ==== 4.2. AVCC3V0 ==== | ||
+ | |||
+ | The analog supply AVCC3V0 is built from VCC3V3 using IC22, an [[https:// | ||
+ | |||
+ | * Input voltage supply range: 2.3 V to 5.5 V | ||
+ | * 300 mA maximum output current | ||
+ | * Fixed and adjustable output voltage versions | ||
+ | * Very low dropout voltage: 85 mV at 300 mA load | ||
+ | * Low quiescent current: 45 µA at no load | ||
+ | * Low shutdown current: <1 µA | ||
+ | * Initial accuracy: ±1% accuracy | ||
+ | * Up to 31 fixed-output voltage options available from | ||
+ | * 1.75 V to 3.3 V | ||
+ | * Adjustable-output voltage range | ||
+ | * 0.8 V to 5.0 V (ADP123) | ||
+ | * Excellent PSRR performance: | ||
+ | * Excellent load/line transient response | ||
+ | * Optimized for small 1.0 μF ceramic capacitors | ||
+ | * Current limit and thermal overload protection | ||
+ | * Logic controlled enable | ||
+ | * Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ==== 4.3. AVCC4V5 ==== | ||
+ | |||
+ | The analog supply AVCC4V5 is built from VCC5V0 using IC19, an [[https:// | ||
+ | |||
+ | * Input voltage supply range: 2.3 V to 5.5 V | ||
+ | * 300 mA maximum output current | ||
+ | * Fixed and adjustable output voltage versions | ||
+ | * Very low dropout voltage: 85 mV at 300 mA load | ||
+ | * Low quiescent current: 45 µA at no load | ||
+ | * Low shutdown current: <1 µA | ||
+ | * Initial accuracy: ±1% accuracy | ||
+ | * Up to 31 fixed-output voltage options available from | ||
+ | * 1.75 V to 3.3 V | ||
+ | * Adjustable-output voltage range | ||
+ | * 0.8 V to 5.0 V (ADP123) | ||
+ | * Excellent PSRR performance: | ||
+ | * Excellent load/line transient response | ||
+ | * Optimized for small 1.0 μF ceramic capacitors | ||
+ | * Current limit and thermal overload protection | ||
+ | * Logic controlled enable | ||
+ | * Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ==== 4.4. AVCC-2V5 ==== | ||
+ | |||
+ | The AVCC-2V5 analog power supply is implemented with the [[http:// | ||
+ | |||
+ | * 1.2 A maximum load current | ||
+ | * ±2% output accuracy over temperature range | ||
+ | * 1.4 MHz switching frequency | ||
+ | * High efficiency up to 91% | ||
+ | * Current-mode control architecture | ||
+ | * Output voltage from 0.8 V to 0.85 × VIN | ||
+ | * Automatic PFM/PWM mode switching | ||
+ | * Integrated high-side MOSFET | ||
+ | * Internal compensation and soft start | ||
+ | * Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD) | ||
+ | * Available in ultrasmall, 6-lead TSOT package | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | |||
+ | ===== 5. The SYZYGY™ Connector ===== | ||
+ | |||
+ | The SYZYGY™ connector in provides the interface with the carrier board. The used signals are: | ||
+ | * Power rails | ||
+ | * VCC5V0 | ||
+ | * VCC3V3 | ||
+ | * VADJ - needs to be set by the carrier board to 1.8V | ||
+ | * GND | ||
+ | * Shield | ||
+ | * SYZYGY™ I2C bus: | ||
+ | * MCU_SCLUSCK | ||
+ | * MCU_SDA_MOSI | ||
+ | * ADC differential input clock | ||
+ | * CLKIN_ADC_P | ||
+ | * CLKIN_ADC_N | ||
+ | * ADC single ended output clock: | ||
+ | * CLKOUT_ADC (coupled with GND in the differential P2C pair) | ||
+ | * R_GA for geographical address identification | ||
+ | * SYNC_ADC for ADC internal clock divider synchronization | ||
+ | * ADC data bus: DOUT_ADC_0...13 | ||
+ | * ADC SPI bus: | ||
+ | * CS_SC1n | ||
+ | * SCLK_SC | ||
+ | * SDIO_SC | ||
+ | * relay control | ||
+ | * SCx_yy_z | ||
+ | |||
+ | {{reference: | ||
+ | // | ||
+ | |||
+ | ===== 6. The SYZYGY™ compatibility table ===== | ||
+ | |||
+ | // | ||
+ | ^ Parameter | ||
+ | | Maximum 5V supply current | ||
+ | | Maximum 3.3V supply current | ||
+ | | VIO supply voltage | ||
+ | | Maximum VIO supply current | ||
+ | | Total number of I/O | 28 | | ||
+ | | Number of differential I/O pairs | 0 | | ||
+ | | Width | Single | ||
+ | |||
+ | |||
+ | |||
+ | **Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania** |