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zmod:digitizer:reference-manual [2022/10/10 06:34] – [2.5. Scope ADC] Mircea Dabacan | zmod:digitizer:reference-manual [2024/01/09 04:02] (current) – [Table] Laszlo Attila Kovacs | ||
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+ | ====== Zmod Digitizer Reference Manual ====== | ||
+ | |||
+ | The Digilent Zmod Digitizer is a SYZYGY™ ((The “SYZYGY™ ” mark is owned by Opal Kelly.))compatible pod containing a dual-channel ADC and the associated front end. The Zmod Digitizer is intended to be used with any SYZYGY™ compatible carrier board having the required capabilities. | ||
+ | |||
+ | {{Digilent Image Gallery | ||
+ | | image = {{zmod/ | ||
+ | | image = {{zmod/ | ||
+ | | image = {{zmod/ | ||
+ | }} | ||
+ | |||
+ | ~~REFNOTES~~ | ||
+ | ===== Features ===== | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Features/ | ||
+ | | ADC | AD9648BCPZ-125 | ||
+ | | Input Channels | ||
+ | | Input Range | ±1 V | | ||
+ | | Resolution [bits] | ||
+ | | Absolute Resolution | ||
+ | | Accuracy [% of Input Range] [(when using the appropriate calibration coefficients, | ||
+ | | Sample Rate - Max [MS/ | ||
+ | | Analog Bandwidth @ 3 dB | 60 MHz | | ||
+ | | Analog Bandwidth @ 0.5 dB | 20 MHz | | ||
+ | | Analog Bandwidth @ 0.1 dB | 8 MHz | | ||
+ | | Input Impedance [MΩ] | 1 MΩ < | ||
+ | |||
+ | ~~REFNOTES~~ | ||
+ | ===== 1. Architectural Overview and Block Diagram ===== | ||
+ | |||
+ | This document describes the Zmod Digitizer' | ||
+ | |||
+ | Zmod Digitizer' | ||
+ | |||
+ | The **Analog Input** block has a similar structure and behavior to a scope frontend, for that reason some of the signals in this circuitry use the " | ||
+ | |||
+ | * The** Analog Input (Scope) ** instrument block includes: | ||
+ | * **Input Divider**: high bandwidth input adapter/ | ||
+ | * **Buffer and filter**: high impedance buffer and anti-alias filter | ||
+ | * **Driver**: provides appropriate signal levels and protection to the ADC. | ||
+ | * **Scope Reference**: | ||
+ | * **Clock Generator**: | ||
+ | * **ADC**: the analog-to-digital converter for both digitizer channels. | ||
+ | * The **Power Supplies and Control** block generates all internal supply voltages. | ||
+ | * The **MCU** works as an I2C memory for two different purposes: | ||
+ | * The **DNA** includes the standard [[https:// | ||
+ | * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the Input Divider, the Zmod Digitizer includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data. | ||
+ | |||
+ | In the sections that follow, schematics are not shown separately for identical blocks. | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | ---- | ||
+ | ===== 2. Analog Input ===== | ||
+ | |||
+ | [[# | ||
+ | |||
+ | |||
+ | {{ : | ||
+ | // | ||
+ | ==== 2.1. Input Divider ==== | ||
+ | C< | ||
+ | C< | ||
+ | |||
+ | The input divider provides: | ||
+ | * Analog input impedance = 1 MOhm || 5 pF | ||
+ | * a 0.25 attenuation | ||
+ | * Controlled capacitance, | ||
+ | * Constant attenuation over a large frequency range (trimmer adjusted) | ||
+ | The maximum voltage rating for analog inputs is limited to: | ||
+ | |||
+ | $$-50V< | ||
+ | |||
+ | The DC gain is: $$\frac {V_{DIV1}}{V_{SCOPE1-SMA}}=\frac {R_5 + R_6}{R_3+R_5 + R_6}=0.25\label{2}\tag{2}$$ | ||
+ | |||
+ | The nominal input voltage range is: $$-1V \le V_{SCOPE1-SMA} \le 1V \label{3}\tag{3}$$ | ||
+ | |||
+ | The divider equivalent impedance is: | ||
+ | |||
+ | $$R_{ech} = R_3 + R_5 + R_6 = 1Mohm\label{4}\tag{4}$$ | ||
+ | |||
+ | Experiments shown that there is significant parasitic capacity in the V< | ||
+ | |||
+ | $$C_2*R_3 = (\frac{C_3*C_4}{C_3+C_4} + C_P)*(R_5+R_6)\label{5}\tag{5}$$ | ||
+ | |||
+ | The equivalent capacitance of the input divider (SCOPE1_SMA node) is: | ||
+ | |||
+ | $$C_{ech} = 5.1pF\label{6}\tag{6}$$ | ||
+ | |||
+ | |||
+ | |||
+ | ==== 2.2. Buffer and Filter ==== | ||
+ | |||
+ | The buffer stage provides very high impedance as load for the input divider. The buffer has no internal input protection diode, so D1 was added. The anti-alias filter has a bandwidth of 60MHz. | ||
+ | |||
+ | ==== 2.3. Driver ==== | ||
+ | |||
+ | The ADC driver is used for: | ||
+ | * Driving the differential inputs of the ADC (with low impedance outputs) | ||
+ | * Providing the common mode voltage for the ADC | ||
+ | * ADC protection. | ||
+ | |||
+ | The total gain of the buffer, amplifier and driver is: | ||
+ | |||
+ | $$\frac {V_{ADC\; | ||
+ | |||
+ | ---- | ||
+ | |||
+ | |||
+ | ==== 2.4. Scope Reference ==== | ||
+ | |||
+ | {{zmod: | ||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | The scope reference stage generates the 1.25 V reference voltage which is decreased to 1 V, buffered by IC7B and provided to the ADC. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ==== 2.5. ADC ==== | ||
+ | |||
+ | The Zmod Digitizer uses a dual channel, high speed, low power, 14-bit, 125 MS/s ADC, as shown in [[# | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | The differential inputs are impedance matched with the driver stage. | ||
+ | |||
+ | The differential clock is AC-coupled and the line is impedance matched. | ||
+ | The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | ||
+ | |||
+ | The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8 V by the SYZYGY™ voltage V< | ||
+ | |||
+ | The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data. | ||
+ | ---- | ||
+ | |||
+ | ==== 2.6. Clock Generator ==== | ||
+ | |||
+ | IC5 in the figure below is a low jitter clock generator: CDCE6214. It has a PLL loop, with divider and multiplier registers, for programmable output frequencies. | ||
+ | An input MUX can select between two possible clock sources: | ||
+ | * Zmod Digitizer uses a crystal for a low jitter clock source at CLKIN_XTAL pins. | ||
+ | * As an alternative, | ||
+ | OUT4 pins generate the LVDS clock for the ADC, CLKIN_ADC. | ||
+ | |||
+ | The circuit is programmed via a dedicated I2C bus, which is not the standard SYZYGY I2C bus used to communicate with the ADN MCU of the Zmod. | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | |||
+ | |||
+ | ==== 2.7 Signal Scaling ==== | ||
+ | |||
+ | The nominal differential ADC input voltage range is: | ||
+ | |||
+ | $$-1V< | ||
+ | |||
+ | The total analog gain (from the SMA connectors to the ADC inputs) is: | ||
+ | |||
+ | $$Analog\; gain = \frac{V_{ADC\; | ||
+ | |||
+ | Considering the ADC input voltage range shown in \ref{8}: | ||
+ | |||
+ | $$ -1.055V< | ||
+ | |||
+ | To cover component value tolerances and to allow software calibration, | ||
+ | |||
+ | $$ -1V< | ||
+ | |||
+ | With the 14-bit ADC, the absolute resolution is (see [[# | ||
+ | |||
+ | $$ \frac{2.11V}{2^{n}}=0.13mV\label{12}\tag{12}$$ | ||
+ | |||
+ | For V< | ||
+ | |||
+ | $$V_{in} = \frac{N \cdot Range \cdot (1+CG)}{2^{n-1}} + CA \label{13}\tag{13}$$ | ||
+ | |||
+ | were: | ||
+ | * n = 14, the number of bits of the ADC | ||
+ | * V< | ||
+ | * N = the n bit, 2's complement integer number returned by the ADC | ||
+ | * Range = 1.055 V = the ideal Range of the input stage (approximation of the values in equation \ref{9}): | ||
+ | * CA = calibration Additive constant (for the appropriate channel and frequency; see paragraph 2.8 and [[# | ||
+ | * CG = calibration Gain constant (for the appropriate channel and frequency; see paragraph 2.8 and [[# | ||
+ | |||
+ | |||
+ | ==== 2.8 Sampling Frequency Characteristics ==== | ||
+ | |||
+ | The S&H capacitance at the input of the ADC, together with the PCB inductance form a resonant circuitry excited by the sampling frequency. In terms of ADC numerical results, this generates gain and offset errors which are dependent on the Sampling frequency. To minimize the effect, two solutions are implemented: | ||
+ | * R10 and R13 values were chosen to optimally damp the oscillation at the ADC differential input. | ||
+ | * The calibration constants are computed and stored in the DNA MCU for 7 different sampling frequencies (122.88 MHz, 50 MHz, 80 MHz, 100 MHz, 110 MHz, 120 MHz, and 125 MHz). For applications requiring high accuracy, the appropriate set of calibration constants should be used, as explained in the Signal Scaling paragraph. For less sensitive applications, | ||
+ | |||
+ | The figure below shows typical errors for the two cases. | ||
+ | * The input voltage for both channels is set to a DC value of -0.9 V (left), 0 V, (middle) and 0.9 V (right) | ||
+ | * Multiple acquisitions are performed at sampling frequencies between 50 MHz and 125 MHz.The absolute error between the measured value and ideal input voltage is displayed as a function of sampling frequency. | ||
+ | * The graphs in the upper row use the set of constants that were computed at a sampling frequency of 122.88 MHz. | ||
+ | * The graphs in the lower row interpolate the 7 sets of constants when browsing the actual sampling frequency. | ||
+ | |||
+ | {{zmod: | ||
+ | {{zmod: | ||
+ | // | ||
+ | Zmod Digitizer calibrated at 122.88 MHz (top), respectively at 7 different frequencies (bottom). | ||
+ | Notice the vertical scaling difference between the top and bottom graphs. }}// | ||
+ | |||
+ | ==== 2.9 Analog Spectral Characteristics ==== | ||
+ | |||
+ | [[# | ||
+ | The signal swept from 800 kHz to 80 MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were further processed to display the input stage frequency characteristics, | ||
+ | |||
+ | The 3 dB bandwidth is 60+ MHz. The 0.5 dB bandwidth is 20 MHz and the 0.1 dB bandwidth is 8 MHz. | ||
+ | |||
+ | The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The bandwidth @ 0.5 dB, means a flatness error of a max 5.6%, while bandwidth @ 0.1 dB means flatness error of a max 1.1%. | ||
+ | |||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | ---- | ||
+ | |||
+ | |||
+ | ===== 3. MCU ===== | ||
+ | |||
+ | The [[https:// | ||
+ | |||
+ | The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as " | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | * Program Memory Type: Flash | ||
+ | * Program Memory Size (KB): 4 | ||
+ | * CPU Speed (MIPS/ | ||
+ | * SRAM Bytes: 256 | ||
+ | * Data EEPROM/HEF (bytes): 256 | ||
+ | * Digital Communication Peripherals: | ||
+ | * Capture/ | ||
+ | * Timers: 1 x 8-bit, 1 x 16-bit | ||
+ | * Number of Comparators: | ||
+ | * Temperature Range (C): -40 to 85 | ||
+ | * Operating Voltage Range (V): 1.8 to 5.5 | ||
+ | * Pin Count: 14 | ||
+ | * Low Power: Yes | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Address | ||
+ | | 0x8000 - 0x80FF | ||
+ | | 0x8100 - 0x817F | ||
+ | | 0x8180 - 0x83FF | ||
+ | ==== 3.1. SYZYGY™ DNA ==== | ||
+ | |||
+ | The Zmod Digitizer is compliant with [[https:// | ||
+ | |||
+ | // | ||
+ | |||
+ | ^ Contents | ||
+ | | DNA full data length | ||
+ | | DNA header length | ||
+ | | SYZYGY DNA major version | ||
+ | | SYZYGY DNA minor version | ||
+ | | Required SYZYGY DNA major version | ||
+ | | Required SYZYGY DNA minor version | ||
+ | | Maximum operating 5V load (mA) | uint16 | ||
+ | | Maximum operating 3.3V load (mA) | uint16 | ||
+ | | Maximum VIO load (mA) | uint16 | ||
+ | | Attribute flags | uint16 | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Minimum operating VIO (10 mV steps) | ||
+ | | Maximum operating VIO (10 mV steps) | ||
+ | | Manufacturer name length | ||
+ | | Product name length | ||
+ | | Product model / Part number length | ||
+ | | Product version / revision length | ||
+ | | Serial number length | ||
+ | | RESERVED | ||
+ | | CRC-16 (most significant byte) | uint8 | 1 | CRC computed over the addresses 0x8000-0x8025: | ||
+ | | CRC-16 (least significant byte) | uint8 | 1 | CRC computed over the addresses 0x8000-0x8025: | ||
+ | | END DATA HEADER | ||
+ | | Manufacturer name | string | ||
+ | | Product name | string | ||
+ | | Product model / Part number | ||
+ | | Product version / revision | ||
+ | | Serial number | ||
+ | | Product ID | uint32 | ||
+ | |||
+ | ==== 3.2. Calibration Memory ==== | ||
+ | |||
+ | The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, | ||
+ | |||
+ | * 0.1% resistors and 1% capacitors in all the critical analog signal paths | ||
+ | * Capacitive trimmers for balancing the Input Divider and Gain Selection | ||
+ | * No other mechanical trimmers (as these are big, expensive, unreliable and affected by vibrations, aging, and temperature drifts) | ||
+ | * Software calibration, | ||
+ | * User software calibration, | ||
+ | |||
+ | Software calibration is performed on each device as a part of the manufacturing test. Reference signals are connected to the inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod Digitizer device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user to perform in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible. | ||
+ | |||
+ | The Software reads the calibration parameters from the Zmod Digitizer MCU via the I2C bus and uses them to correct the acquired signals. | ||
+ | The structure of the calibration data is shown below: | ||
+ | |||
+ | // | ||
+ | ^ Heading 1 | ** Name ** ^ Size (Bytes) | ||
+ | | Magic ID | ||
+ | | Calibration Time | ||
+ | | Frequency[0] | ||
+ | | Frequency[1] | ||
+ | | Frequency[2] | ||
+ | | Frequency[3] | ||
+ | | Frequency[4] | ||
+ | | Frequency[5] | ||
+ | | Frequency[6] | ||
+ | | unused | ||
+ | | Channel 1 Gain F[0] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[0] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[0] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[0] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[1] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[1] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[1] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[1] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[2] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[2] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[2] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[2] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[3] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[3] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[3] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[3] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[4] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[4] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[4] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[4] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[5] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[5] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[5] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[5] | CA | 4 | float32 | ||
+ | | Channel 1 Gain F[6] | CG | 4 | float32 | ||
+ | | Channel 1 Offset F[6] | CA | 4 | float32 | ||
+ | | Channel 2 Gain F[6] | CG | 4 | float32 | ||
+ | | Channel 2 Offset F[6] | CA | 4 | float32 | ||
+ | | CRC | | 1 | uchar | 0x817F | ||
+ | |||
+ | |||
+ | // | ||
+ | |||
+ | ^ | ||
+ | | 0x7000 - 0x707F | ||
+ | | 0x7080 - 0x70FF | ||
+ | |||
+ | At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write any other number to the magic address. | ||
+ | |||
+ | // | ||
+ | ^ Magic Number | ||
+ | | 0xD2 | ||
+ | |||
+ | |||
+ | ---- | ||
+ | |||
+ | |||
+ | ===== 4. Power Supplies and Control ===== | ||
+ | |||
+ | This block includes the internal power supplies. | ||
+ | |||
+ | The Zmod Digitizer gets the digital rails from the carrier board, via the SYZYGY connector: | ||
+ | |||
+ | * VCC5V0 - used for analog supplies | ||
+ | * VCC3V3 - used for the MCU and analog supplies | ||
+ | * Vadj = 1.8 V - used for the ADC digital rail | ||
+ | |||
+ | |||
+ | The internal analog rails sequence is: | ||
+ | |||
+ | * AVCC1V8 - ADC analog rail | ||
+ | * AVCC3V0 - Buffer, reference voltage, ADC driver | ||
+ | * AVCC-2V5 - Buffer, reference voltage | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | ==== 4.1. AVCC1V8 ==== | ||
+ | |||
+ | The analog supply AVCC1V8 is built from VCC5V0 using IC11, an [[http:// | ||
+ | |||
+ | * Input voltage: 2.3 V to 5.5 V | ||
+ | * Peak efficiency: 95% | ||
+ | * 3 MHz fixed frequency operation | ||
+ | * Typical quiescent current: 24 μA | ||
+ | * Very small solution size | ||
+ | * 6-lead, 1 mm × 1.5 mm WLCSP package | ||
+ | * Fast load and line transient response | ||
+ | * 100% duty cycle low dropout mode | ||
+ | * Internal synchronous rectifier, compensation, | ||
+ | * Current overload and thermal shutdown protections | ||
+ | * Ultra-low shutdown current: 0.2 μA (typical) | ||
+ | * Forced PWM and automatic PWM/PSM modes | ||
+ | |||
+ | |||
+ | ==== 4.2. AVCC3V0 ==== | ||
+ | |||
+ | The analog supply AVCC3V0 is built from VCC3V3 using IC9, an [[https:// | ||
+ | |||
+ | * Input voltage supply range: 2.3 V to 5.5 V | ||
+ | * 300 mA maximum output current | ||
+ | * Fixed and adjustable output voltage versions | ||
+ | * Very low dropout voltage: 85 mV at 300 mA load | ||
+ | * Low quiescent current: 45 µA at no load | ||
+ | * Low shutdown current: <1 µA | ||
+ | * Initial accuracy: ±1% accuracy | ||
+ | * Up to 31 fixed-output voltage options available from | ||
+ | * 1.75 V to 3.3 V | ||
+ | * Adjustable-output voltage range | ||
+ | * 0.8 V to 5.0 V (ADP123) | ||
+ | * Excellent PSRR performance: | ||
+ | * Excellent load/line transient response | ||
+ | * Optimized for small 1.0 μF ceramic capacitors | ||
+ | * Current limit and thermal overload protection | ||
+ | * Logic-controlled enable | ||
+ | * Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ==== 4.4. AVCC-2V5 ==== | ||
+ | |||
+ | The AVCC-2V5 analog power supply is implemented with the [[http:// | ||
+ | |||
+ | * 1.2 A maximum load current | ||
+ | * ±2% output accuracy over temperature range | ||
+ | * 1.4 MHz switching frequency | ||
+ | * High efficiency up to 91% | ||
+ | * Current-mode control architecture | ||
+ | * Output voltage from 0.8 V to 0.85 × VIN | ||
+ | * Automatic PFM/PWM mode switching | ||
+ | * Integrated high-side MOSFET | ||
+ | * Internal compensation and soft start | ||
+ | * Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD) | ||
+ | * Available in ultrasmall, 6-lead TSOT package | ||
+ | |||
+ | |||
+ | |||
+ | ===== 5. The SYZYGY™ Connector ===== | ||
+ | |||
+ | The SYZYGY™ connector in provides the interface with the carrier board. The used signals are: | ||
+ | * Power rails | ||
+ | * VCC5V0 | ||
+ | * VCC3V3 | ||
+ | * VADJ - needs to be set by the carrier board to 1.8V | ||
+ | * GND | ||
+ | * Shield | ||
+ | * SYZYGY™ I2C bus: | ||
+ | * MCU_SCL_USCK | ||
+ | * MCU_SDA_MOSI | ||
+ | * FPGA generated differential clock (alternate for local CDCE clock) | ||
+ | * CLK_PLL_P | ||
+ | * CLK_PLL_N | ||
+ | * ADC single-ended output clock: | ||
+ | * CLKOUT_ADC (coupled with GND in the differential P2C pair) | ||
+ | * R_GA for geographical address identification | ||
+ | * SYNC_ADC for ADC internal clock divider synchronization | ||
+ | * ADC data bus: DOUT_ADC_0...13 | ||
+ | * ADC SPI bus: | ||
+ | * CS_SC1n | ||
+ | * SCLK_SC | ||
+ | * SDIO_SC | ||
+ | * CDCE control signals | ||
+ | * CDCE_REFSEL | ||
+ | * CDCE_HW_SW_CTRL | ||
+ | * CDCE_PDN | ||
+ | * CDCE_GPIO_1 | ||
+ | * CDCE_GPIO_4 | ||
+ | * CDCE I2C bus | ||
+ | * CDCE_SCL | ||
+ | * CDCE_SDA | ||
+ | |||
+ | {{zmod: | ||
+ | // | ||
+ | |||
+ | ===== 6. The SYZYGY™ compatibility table ===== | ||
+ | |||
+ | // | ||
+ | ^ Parameter | ||
+ | | Maximum 5V supply current | ||
+ | | Maximum 3.3V supply current | ||
+ | | VIO supply voltage | ||
+ | | Maximum VIO supply current | ||
+ | | Total number of I/O | 28 | | ||
+ | | Number of differential I/O pairs | 0 | | ||
+ | | Width | Single | ||
+ | |||
+ | |||
+ | |||
+ | **Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania** |