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vivado:library [2020/05/15 20:44] – [IPcores] Monica Ignatvivado:library [2020/05/15 20:55] – [IPcores] Monica Ignat
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     * [[https://github.com/Digilent/vivado-library/tree/master/ip/AXI_DPTI_1.0|AXI_DPTI_1.0]] - this core implements an interface between DPTI and AXI4 Stream. The interface will be controlled using Microblaze via control and status registers and it will theoretically be capable of speeds up to 480 megabits per second. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-      * [[https://github.com/Digilent/vivado-library/tree/master/ip/AXI_DPTI_1.0|AXI_DPTI_1.0]] - this core implements an interface between DPTI and AXI4 Stream. The interface will be controlled using Microblaze via control and status registers and it will theoretically be capable of speeds up to 480 megabits per second. More details about its functionality can be found in the [[https://github.com/Digilent/vivado- 
 library/blob/master/ip/AXI_DPTI_1.0/doc/AXI%20DPTI.pdf|documentation]] library/blob/master/ip/AXI_DPTI_1.0/doc/AXI%20DPTI.pdf|documentation]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_CSI_2_RX|MIPI_CSI_2_RX]] - This IP is compatible with CSI-2 1.0 specifications and supports decoding selected pixel formats and packing data into an AXI-Stream. It pairs up with a MIPI D-PHY Receiver IP over the standard PHY Protocol Interface (PPI) to source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_CSI_2_RX|MIPI_CSI_2_RX]] - This IP is compatible with CSI-2 1.0 specifications and supports decoding selected pixel formats and packing data into an AXI-Stream. It pairs up with a MIPI D-PHY Receiver IP over the standard PHY Protocol Interface (PPI) to source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/MIPI_CSI_2_RX/docs/mipi_csi_2_rx.pdf|documentation]] 
-library/blob/master/ip/MIPI_CSI_2_RX/docs/mipi_csi_2_rx.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_D_PHY_RX|MIPI_D_PHY_RX]] - This IP is compatible with D-PHY 1.0 specifications and serves as the lowest layer of the high-speed source-synchronous interface defined by MIPI Alliance. It pairs up with a MIPI CSI-2 Receiver IP over the standard PHY Protocol Interface (PPI) to receive data from an image sensor and source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/MIPI_D_PHY_RX/docs/mipi_d_phy_rx.pdf|documentation]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/MIPI_D_PHY_RX|MIPI_D_PHY_RX]] - This IP is compatible with D-PHY 1.0 specifications and serves as the lowest layer of the high-speed source-synchronous interface defined by MIPI Alliance. It pairs up with a MIPI CSI-2 Receiver IP over the standard PHY Protocol Interface (PPI) to receive data from an image sensor and source a video subsystem. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-library/blob/master/ip/MIPI_D_PHY_RX/docs/mipi_d_phy_rx.pdf|documentation]]+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/MotorFeedback_1.0|MotorFeedback_1.0]]      * [[https://github.com/Digilent/vivado-library/tree/master/ip/MotorFeedback_1.0|MotorFeedback_1.0]] 
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_1.0|PWM_1.0]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_1.0|PWM_1.0]]
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     * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_Analyzer_1.0|PWM_Analyzer_1.0]]      * [[https://github.com/Digilent/vivado-library/tree/master/ip/PWM_Analyzer_1.0|PWM_Analyzer_1.0]] 
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/Pmods|Pmods]] - It contains a set of IPs for most of the Digilent Pmods     * [[https://github.com/Digilent/vivado-library/tree/master/ip/Pmods|Pmods]] - It contains a set of IPs for most of the Digilent Pmods
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Sync_v1_0|Sync_v1_0]] - It provides clock domain crossing for signals where variable crossing latency does not affect functionality.   +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/Sync_v1_0|Sync_v1_0]] - It provides clock domain crossing for signals where variable crossing latency does not affect functionality. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/Sync_v1_0/docs/Sync_v1_0.pdf|documentation]]
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-library/blob/master/ip/Sync_v1_0/docs/Sync_v1_0.pdf|documentation]]+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/Zmods|Zmods]] - It contains a set of low level controller for both ZmodADC1410 and ZmodDAC1411, as well as their corresponding AXI interface adapters.     * [[https://github.com/Digilent/vivado-library/tree/master/ip/Zmods|Zmods]] - It contains a set of low level controller for both ZmodADC1410 and ZmodDAC1411, as well as their corresponding AXI interface adapters.
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_dynclk_v1_1|axi_dynclk_v1_1]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_dynclk_v1_1|axi_dynclk_v1_1]]
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_i2s_adi_1.2|axi_i2s_adi_1.2]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_i2s_adi_1.2|axi_i2s_adi_1.2]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_ps2_1.0|axi_ps2_1.0]] - The purpose of this IP is to implement a software controllable PS/2 host controller. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/axi_ps2_1.0|axi_ps2_1.0]] - The purpose of this IP is to implement a software controllable PS/2 host controller. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/axi_ps2_1.0/doc/AXI%20PS2.pdf|documentation]]
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +
-library/blob/master/ip/axi_ps2_1.0/doc/AXI%20PS2.pdf|documentation]]+
     * [[https://github.com/Digilent/vivado-library/tree/master/ip/clock_forwarder|clock_forwarder]]     * [[https://github.com/Digilent/vivado-library/tree/master/ip/clock_forwarder|clock_forwarder]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb|dvi2rgb]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel inputs as defined in DVI 1.0 specs for Sink devices. It decodes the video stream and outputs 24-bit RGB video data along with the pixel clock and synchronization signals recovered from the TMDS link. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/dvi2rgb|dvi2rgb]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel inputs as defined in DVI 1.0 specs for Sink devices. It decodes the video stream and outputs 24-bit RGB video data along with the pixel clock and synchronization signals recovered from the TMDS link. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_contrast_stretch_1_0|hls_contrast_stretch_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the contrast factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_contrast_stretch_1_0/doc/HLS_Contrast_Stretch_v1_0.pdf|documentation]] 
-library/blob/master/ip/dvi2rgb/docs/dvi2rgb.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_gamma_correction_1_0|hls_gamma_correction_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the gamma factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_gamma_correction_1_0/doc/HLS_Gamma%20Correction_v1_0.pdf|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_contrast_stretch_1_0|hls_contrast_stretch_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the contrast factor. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]] 
-library/blob/master/ip/hls_contrast_stretch_1_0/doc/HLS_Contrast_Stretch_v1_0.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]] 
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_gamma_correction_1_0|hls_gamma_correction_1_0]] - The IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the gamma factor. +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]] 
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-  +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]] 
-library/blob/master/ip/hls_gamma_correction_1_0/doc/HLS_Gamma%20Correction_v1_0.pdf|documentation]] +    * [[https://github.com/Digilent/vivado-library/tree/master/ip/video_scaler|video_scaler]] - This IP takes video frames of arbitrary resolution over a slave AXI-Stream interface, resizes them to an arbitrary output resolution and outputs on a master AXI-Stream interface. It has an AXI4-Lite interface for control. More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/video_scaler/doc/video_scaler.pdf|documentation]]
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/hls_saturation_enhance_1_0/doc/HLS_Saturation_Enhancement_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dpvid_v1_0/docs/rgb2dpvid_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2dvi/docs/rgb2dvi.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC.  +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/rgb2vga_v1_0/docs/rgb2vga_v1_0.pdf|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/usb2device_v1_0/docs/USB_Device.docx|documentation]] +
-    * [[https://github.com/Digilent/vivado-library/tree/master/ip/video_scaler|video_scaler]] - This IP takes video frames of arbitrary resolution over a slave AXI-Stream interface, resizes them to an arbitrary output resolution and outputs on a master AXI-Stream interface. It has an AXI4-Lite interface for control. +
-More details about its functionality can be found in the [[https://github.com/Digilent/vivado-library/blob/master/ip/video_scaler/doc/video_scaler.pdf|documentation]]+
 ===== Interfaces ===== ===== Interfaces =====