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test-and-measurement:digital-discovery:demos:zynq-qspi-boot [2022/03/28 20:47] – Update xilinx links Arthur Browntest-and-measurement:digital-discovery:demos:zynq-qspi-boot [2023/02/09 01:38] (current) – external edit 127.0.0.1
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   * Digital Discovery   * Digital Discovery
   * Zynq board with flash   * Zynq board with flash
 +    * **Note:** //This document was written using a Zybo Z7 of a revision earlier than D.0.//
   * SOIC clip if available   * SOIC clip if available
   * Wires   * Wires
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 When deciding how to tackle this problem, there were two smaller Instrumentation devices that have a Logic Analyzer, the Analog Discovery 2 and Digital Discovery. There were two reasons for using the Digital Discovery instead of the Analog Discovery 2. The first reason was that the QSPI transactions can take place at much higher clock speeds, over 100 MHz, so having an adequate sample rate is very important. The other reason was that because of the 512 MB DDR memory that the Digital Discovery has, it can perform very large acquisitions. When deciding how to tackle this problem, there were two smaller Instrumentation devices that have a Logic Analyzer, the Analog Discovery 2 and Digital Discovery. There were two reasons for using the Digital Discovery instead of the Analog Discovery 2. The first reason was that the QSPI transactions can take place at much higher clock speeds, over 100 MHz, so having an adequate sample rate is very important. The other reason was that because of the 512 MB DDR memory that the Digital Discovery has, it can perform very large acquisitions.
-====== Step 1: Connecting the Digital Discovery  ======+===== Step 1: Connecting the Digital Discovery  =====
  
 The following connections are required: The following connections are required:
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 Make sure to check for signal integrity/cross talk when using cables like this. In some cases, twisting a signal with a GND wire will be needed (in this case it was the blue cs wire). Make sure to check for signal integrity/cross talk when using cables like this. In some cases, twisting a signal with a GND wire will be needed (in this case it was the blue cs wire).
-====== Step 2: QSPI script  ======+===== Step 2: QSPI script  =====
  
 A custom interpreter is used which will translate the QSPI signals into data. This is activated by adding a "Custom" channel from the Logic instrument in WaveForms. Below is the js code which interprets the QSPI signals. A custom interpreter is used which will translate the QSPI signals into data. This is activated by adding a "Custom" channel from the Logic instrument in WaveForms. Below is the js code which interprets the QSPI signals.
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 In parallel with this interpreter, we can also use a standard SPI in order to see instructions which are not sent via QSPI, for example the first read instruction. In parallel with this interpreter, we can also use a standard SPI in order to see instructions which are not sent via QSPI, for example the first read instruction.
-====== Step 3: Trigger and acquisition  ======+===== Step 3: Trigger and acquisition  =====
  
 Although the maximum QSPI clock frequency is about 100 MHz, when booting, a maximum frequency of 25 MHz is used. Also, the entire boot transfer takes about 700 ms. Because of this, both a large number of samples and a decent sample rate are needed, and this is where the Digital Discovery comes in handy. 268 million samples at 200 MHz would translate into a ~1.3 second frame.  Although the maximum QSPI clock frequency is about 100 MHz, when booting, a maximum frequency of 25 MHz is used. Also, the entire boot transfer takes about 700 ms. Because of this, both a large number of samples and a decent sample rate are needed, and this is where the Digital Discovery comes in handy. 268 million samples at 200 MHz would translate into a ~1.3 second frame. 
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 Notice the short pause near the left end of the acquisition, that is where the clock frequency changes from 5.4 MHz to 25 MHz. Notice the short pause near the left end of the acquisition, that is where the clock frequency changes from 5.4 MHz to 25 MHz.
-====== Step 4: Boot transfers ====== +===== Step 4: Boot transfers ===== 
-There are two documents that need to be read in order to understand what the data transfers represent. One is the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq TRM]] and the other one is the [[https://www.google.ro/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwjTgJvg7uDVAhVI6xQKHfqpA74QFggmMAA&url=http%3A%2F%2Fwww.cypress.com%2Ffile%2F177966%2Fdownload&usg=AFQjCNGhj1bFGD6gfZGYWPR6pdwql2Oc3w|flash memory's datasheet]]. +There are two documents that need to be read in order to understand what the data transfers represent. One is the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq TRM]] and the other one is the [[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17|flash memory's datasheet]]. 
  
 The instructions sent from the Zynq to the flash memory are always sent via SPI using D0. The first instruction sent is 0x03 0x00 0x00 0x20 which means SPI READ from address 0x20 and the reply is also received via SPI using D1, 0x66 0x55 0x99 0xaa. The flash read instruction is explained on page 85 of the datasheet. The instructions sent from the Zynq to the flash memory are always sent via SPI using D0. The first instruction sent is 0x03 0x00 0x00 0x20 which means SPI READ from address 0x20 and the reply is also received via SPI using D1, 0x66 0x55 0x99 0xaa. The flash read instruction is explained on page 85 of the datasheet.