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sume:refmanual [2016/04/11 16:43] – Marthasume:refmanual [2022/03/28 21:59] (current) – Update xilinx links Arthur Brown
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 Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications. Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.
  
-The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[http://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses [[http://www.xilinx.com/support/university/donation-program.html|here]].+The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[https://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses [[https://www.xilinx.com/support/university/donation-program.html|here]].
  
 A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1.  A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1.