Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| sume:refmanual [2015/04/07 20:24] – [FPGA Configuration] Martha | sume:refmanual [2022/03/28 21:59] (current) – Update xilinx links Arthur Brown | ||
|---|---|---|---|
| Line 12: | Line 12: | ||
| Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications. | Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications. | ||
| - | The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[http:// | + | The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[https:// |
| A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1. | A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1. | ||
| Line 37: | Line 37: | ||
| * Four globally unique MAC addresses | * Four globally unique MAC addresses | ||
| * USB-UART | * USB-UART | ||
| - | * I2C Pmod Connector | + | * I2C Pmod Port |
| * Expansion Connectors | * Expansion Connectors | ||
| * QTH Connector (8 GTH transceivers) | * QTH Connector (8 GTH transceivers) | ||
| * One HPC FMC Connector (10 GTH transceivers and 68 User I/Os) | * One HPC FMC Connector (10 GTH transceivers and 68 User I/Os) | ||
| - | * One 12-pin Pmod Connector | + | * One 12-pin Pmod Port (8 User I/Os) |
| * Programming | * Programming | ||
| * Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface) | * Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface) | ||
| Line 286: | Line 286: | ||
| === DDR3 SODIMM === | === DDR3 SODIMM === | ||
| - | The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), | + | The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM, which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), |
| === QDRII+ SRAM === | === QDRII+ SRAM === | ||
| - | Three Cypress CY7C25652KV18 Quad Data Rate II+ (QDRII+) SRAMs are provided for applications that require high speed, low latency memory. Each component provides a 36 bit wide data bus and has a density of 72 Megabits. Common applications include FIFO buffers and look-up tables. The notion of “Quad” data rate comes from the ability to simultaneously read from a unidirectional read port and write to a unidirectional write port on both clock edges. The QDRII+ SRAMs on NetFPGA-SUME board are capable of operating at up to 500MHz to yield data transfer rates of up to 1GT/s per 36-bit wide data bus. The Xilinx Memory Interface Generator (MIG) is able to generate and configure an native interface into the QDRII+ via the user friendly wizard tool. More information regarding the QDRII+ memory part and the Xilinx MIG tool can be found in the Cypress // | + | Three Cypress CY7C25652KV18 Quad Data Rate II+ (QDRII+) SRAMs are provided for applications that require high speed, low latency memory. Each component provides a 36 bit wide data bus and has a density of 72 Megabits. Common applications include FIFO buffers and look-up tables. The notion of "Quad" |
| - | // data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586)// | + | // data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7-Series FPGAs Memory Interface Solutions User Guide (UG586)// |
| - | QDRA and QDRB share FPGA bank 17, which means that in order to access them simultaneously a bank sharing solution must be used that extends beyond the default functionality of the MIG. This solution is still currently being developed. Please refer to //Xilinx Answer Record 41706// for further information. | + | QDRA and QDRB share FPGA bank 17, which means that in order to access them simultaneously, a bank sharing solution must be used that extends beyond the default functionality of the MIG. This solution is still currently being developed. Please refer to //Xilinx Answer Record 41706// for further information. |
| ==== Storage ==== | ==== Storage ==== | ||
| Line 302: | Line 302: | ||
| flash and configuring the FPGA from stored bitstreams, see the section titled " | flash and configuring the FPGA from stored bitstreams, see the section titled " | ||
| - | === Micro-SD | + | === MicroSD |
| - | The micro-SD | + | The microSD |
| ==== SATA ==== | ==== SATA ==== | ||
| - | The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7 Series FPGAs Transceivers Wizard v2.6 User Guide// for more information. | + | The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7-Series FPGAs Transceivers Wizard v2.6 User Guide// for more information. |
| ==== PCI Express ==== | ==== PCI Express ==== | ||
| - | The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA’s high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx 7 Series FPGAs Integrated Block for PCI Express V2.0 (PG054) product guide and 7 Series FPGAs GTX/GTH Transceivers (UG476) user guide for more information. | + | The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA's high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx |
| Line 361: | Line 361: | ||
| === Pmod === | === Pmod === | ||
| - | {{ : | + | {{ : |
| - | The NetFPGA-SUME board also provides a Pmod Connector | + | The NetFPGA-SUME board also provides a Pmod port for peripheral extension. The Pmod port is arranged as a 2x6 vertical, 100-mil female connector that mates with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown above. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. |
| - | The signals on the Pmod connector | + | The signals on the Pmod port are connected to the FPGA via two 4-bit dual-supply bus transceivers (IC1 and IC2, part number SN74AVC4T774) with configurable voltage translation and 3-state outputs. You need to specifically set DIR for each pin to control the signal direction. The bus transceiver is enabled by driving OE pin of the bus transceiver low. |
| ==== Basic I/O ==== | ==== Basic I/O ==== | ||