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sume:refmanual [2015/02/06 04:15] – sbobrowiczsume:refmanual [2022/03/28 21:59] (current) – Update xilinx links Arthur Brown
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 ===== Overview ===== ===== Overview =====
  
-Powered by Xilinx Virtex-7 XC7V690T FPGA, NetFPGA-SUME board is an ideal platform +Powered by Xilinx's Virtex-7 XC7V690T FPGA, the NetFPGA-SUME is an ideal platform for high-performance and high-density networking design.
-for high-performance and high-density networking design.+
  
 32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8), 32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8),
-4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps) and 18 data-rate-adjustable GTH ports through a HPC-FMC connector+4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps), and 18 data-rate-adjustable GTH ports through a HPC-FMC connector
 and a QTH connector. and a QTH connector.
  
-Wide high-speed memory interfaces in the form of 3 x36bit QDRII SRAMs and 2 x64bit DDR3 SODIMMs provide an ideal memory solution for common networking applications.+Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.
  
-The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[http://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses [[http://www.xilinx.com/support/university/donation-program.html|here]]+The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[https://www.xilinx.com/products/design-tools/vivado.html|here]]. Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses [[https://www.xilinx.com/support/university/donation-program.html|here]].
  
-==== Block Diagram ====+A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1. 
  
-{{:sume:net10_blockdiagram.png?direct&500 | NetFPGA SUME Block Diagram}}+{{ :sume:net10_blockdiagram_2.png?direct&700 |NetFPGA SUME Block Diagram}} 
 +//Figure 1. NetFPGA SUME Block diagram.//
  
 ==== Feature List ==== ==== Feature List ====
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     * Xilinx Virtex-7 XC7V690T FFG1761-3     * Xilinx Virtex-7 XC7V690T FFG1761-3
   * Memory   * Memory
-    * Three x36 72Mbits QDR II SRAM (CY7C25652KV18-500BZXC) +    * Two 4GB DDR3 SODIMMs (MT8KTF51264Hz-1G9E1) 
-    * Two 4GB DDR3 SODIMM (MT8KTF51264Hz-1G9E1)     +      * 64 bit wide buses clocked at 850 MHz (1700 mbps) 
-  * Communication Interface +    * Three 72Mbit QDRII+ SRAMs (CY7C25652KV18-500BZXC) 
-    * PCI-E Gen3 x8 (8Gbps/lane) +      * 36 bit wide buses clocked at 500 MHz (1000 mbps) 
-    * Four SFP+ interface (4 GTH transceivers) supporting 10Gbps+  * Storage 
 +    * Two SATA III ports (6 gbps via GTH transceivers) 
 +    * Micro-SD Card Slot 
 +    * Two 512Mbit Micron StrataFlash parallel flash modules (PC28F512G18A) 
 +      * For bitfile storage only 
 +  * Communication Interfaces 
 +    * PCI-E Gen3 x8 supporting 8Gbps/lane 
 +    * Four SFP+ interfaces supporting 10Gbps 
 +      * Four globally unique MAC addresses 
 +    * USB-UART 
 +    * I2C Pmod Port
   * Expansion Connectors   * Expansion Connectors
     * QTH Connector (8 GTH transceivers)     * QTH Connector (8 GTH transceivers)
-    * Two SATA-III ports +    * One HPC FMC Connector (10 GTH transceivers and 68 User I/Os) 
-    * One HPC FMC Connector (10 GTH transceivers) +    * One 12-pin Pmod Port (8 User I/Os)
-    * One 12-pin Pmod Connector+
   * Programming   * Programming
-    * MicroUSB Connector for JTAG programming and debugging (shared with UART interface) +    * Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface) 
-    * Xilinx CPLD XC2C512 for FPGA configuration +    * Xilinx CPLD XC2C512 for FPGA configuration from parallel flash 
-    * Two 512Mbits Micron StrataFlash (PC28F512G18A) for bitfile storage +  * Power Management 
-  * Other I/Os+    * Two Linear Technology Power System Managers (LTC2974) 
 +      * Provide current measuring on all major power rails 
 +  * Other Features
     * User LEDs and Push Buttons     * User LEDs and Push Buttons
-    * Micro-SD Card Slot+    * PROG Push Button for manual FPGA Reset 
 +    * FPGA Configuration LEDs 
 +    * I2C Mux (PCA9548A) for controlling all onboard I2C buses
  
 {{:sume:sume_revc_callout.jpg?direct&600|NetFPGA-SUME Component Callouts}} {{:sume:sume_revc_callout.jpg?direct&600|NetFPGA-SUME Component Callouts}}
- 
- 
 ==== NetFPGA Organization ==== ==== NetFPGA Organization ====
  
 This board is supported by reference designs and IP created by the NetFPGA organization. This board is supported by reference designs and IP created by the NetFPGA organization.
  
-For more information on the NetFPGA organization, go [[http://netfpga.org/2014/#/about/|here]]+For more information on the NetFPGA organization, go [[http://www.netfpga.org|here]].
 ===== Functional Description ===== ===== Functional Description =====
  
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 === Input Supply === === Input Supply ===
  
-The NetFPGA-SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector. The 2 x 4 pin PCI Express Auxiliary Power receptacle (header J14) can accept both 2 x 3 and 2 x 4 pin PCI Express Auxiliary Power Plugs found on a standard ATX power supply. When installed on a PC motherboard, you can plug the 2 x 3 or 2 x 4 pin PCI Express power supply connector directly into header J14. When used in standalone mode (without a PC motherboard), pins 15 and 16 of the main 20 pin connector of the standard ATX power supply must be shorted together as shown in Figure 1. If these pins aren’t shorted together then the power supply will not turn on.+The NetFPGA-SUME receives power via a 2x4 pin PCI Express Auxiliary Power Connector. The 2x4 pin PCI Express Auxiliary Power receptacle (header J14) can accept both 2x3 and 2x4 pin PCI Express Auxiliary Power Plugs found on a standard ATX power supply. When installed on a PC motherboard, you can plug the 2x3 or 2x4 pin PCI Express power supply connector directly into header J14. When used in standalone mode (without a PC motherboard), pins 15 and 16 of the main 20 pin connector of the standard ATX power supply must be shorted together, as shown in Fig. 2. If these pins are not shorted together, then the power supply will not turn on.
  
 {{ :sume:power_1.jpg?direct&400 | Pin 15 and 16 of Standard ATX power supply shorted together}} {{ :sume:power_1.jpg?direct&400 | Pin 15 and 16 of Standard ATX power supply shorted together}}
-//Figure 1. Pin 15 and 16 of Standard ATX power supply shorted together.//+//Figure 2. Pin 15 and 16 of Standard ATX power supply shorted together.//
  
-According to Revision 1.0 of the //PCI Express 225 W/300 W High Power Card Electromechanical Specification// the 2 x 3 pin plug is guaranteed to deliver up to 75 watts of power, while the 2 x 4 pin plug is guaranteed to deliver up to 150 watts of power. While the board may be powered by either a 2 x 3 pin or a 2 x 4 pin PCI Express Auxiliary Power plug, due to the potential for high power consumption, Digilent recommends using a 2 x 4 pin plug to provide power whenever possible.+According to Revision 1.0 of the //PCI Express 225 W/300 W High Power Card Electromechanical Specification//, the 2x3 pin plug is guaranteed to deliver up to 75 Watts of power, while the 2x4 pin plug is guaranteed to deliver up to 150 Watts of power. While the board may be powered by either a 2x3 pin or a 2x4 pin PCI Express Auxiliary Power plug, due to the potential for high power consumption, Digilent recommends using a 2x4 pin plug to provide power whenever possible.
  
 {{ :sume:power_2.png?direct&300 | Power Connector (J14)}} {{ :sume:power_2.png?direct&300 | Power Connector (J14)}}
-//Figure 2. Power Connector (J14).//+//Figure 3. Power Connector (J14).//
  
-Figure 2 describes pin-out of the power connector (header J14) when a 2 x 4 pin or a 2 x 3 pin plug is used. The Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the 2 x 3 pin plug does not include a Sense1 pin it’s possible to determine what type of plug is present, and thus how much power can be consumed.+Figure 3 describes pin-out of the power connector (header J14) when a 2x4 pin or a 2x3 pin plug is used. The Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the 2x3 pin plug does not include a Sense1 pin, it's possible to determine what type of plug is present, and thus how much power can be consumed.
  
-The FPGA logic can determine whether or not a 2 x 4 pin is present by enabling an internal pull-up on pin AW42 and then checking the state of that pin. If logic ‘0’ is seen on AW42 then a 2 x 4 plug is connected and up to 150 watts of power can be drawn. If logic ‘1’ is son on AW42 then a 2 x3 plug is connected, and the board’s power consumption should be limited to 75 watts or less.+The FPGA logic can determine whether or not a 2x4 pin is present by enabling an internal pull-up on pin AW42 and then checking the state of that pin. If logic '0' is seen on AW42, then a 2x4 plug is connected and up to 150 Watts of power can be drawn. If logic '1' is seen on AW42, then a 2x3 plug is connected, and the board's power consumption should be limited to 75 Watts or less.
  
 === Power Supply Topology === === Power Supply Topology ===
  
-The high performance Virtex 7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME require several different supply voltages (supply rails) in order to function. These components also require that the supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal voltages, and rated output currents.+The high performance Virtex-7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME require several different supply voltages (supply rails) in order to function. These components also require that the supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal voltages, and rated output currents.
  
 ^ Supply Rail  ^ Nominal Voltage  ^ Rated Output Current  ^ ^ Supply Rail  ^ Nominal Voltage  ^ Rated Output Current  ^
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 //Table 1. Supply rails, voltages, and currents.// //Table 1. Supply rails, voltages, and currents.//
  
-These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and QDRII+ I/O supplies are powered from the VCC1V5 rail two ferrite beads are also included to prevent high speed switching noise caused by one memory from affecting the other. Figure 4, which can be found on the next page, shows how the various supplies are derived from the input.+These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and QDRII+ I/O supplies are powered from the VCC1V5 rail, two ferrite beads are also included to prevent high speed switching noise caused by one memory from affecting the other. Figure 5 shows how the various supplies are derived from the input.
    
-A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of phase with any of the other clock outputs (see Fig. 3). These out of phase clocks are used as the input clocks for the regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC). The LTC3839, which produces the VCC1V0 supply rail, is a dual phase convertor that directly utilizes the OUT1 clock and indirectly utilizes the OUT4 clock. The use of out of phase clocks reduces the input RMS ripple current.+A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of phase with any of the other clock outputs (see Fig. 4). These out of phase clocks are used as the input clocks for the regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC). The LTC3839, which produces the VCC1V0 supply rail, is a dual phase converter that directly utilizes the OUT1 clock and indirectly utilizes the OUT4 clock. The use of out of phase clocks reduces the input RMS ripple current.
  
 {{ :sume:power_3.png?direct&700 |LTC6909 Clock Output Phase Relationship}} {{ :sume:power_3.png?direct&700 |LTC6909 Clock Output Phase Relationship}}
-//Figure 3. LTC6909 Clock Output Phase Relationship.//+//Figure 4. LTC6909 Clock Output Phase Relationship.//
  
 {{ :sume:power_4.png?direct&700 |Regulator Topology}} {{ :sume:power_4.png?direct&700 |Regulator Topology}}
-//Figure 4. Regulator Topology.//+//Figure 5. Regulator Topology.//
  
 === Power Supply Sequencing and Supervising === === Power Supply Sequencing and Supervising ===
  
-The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular order. The NetFPGA-SUME utilizes two Linear Technology LTC2974’s to ensure that these sequencing requirements are met. Each LTC2974 supports “cascade sequence ON with time-based sequence off” and can monitor the input voltage, four output voltages, four output currents, and four external temperatures using a 16-bit ADC. Additionally, the LTC2974 can margin and trim up to four output voltages using a 10-bit DAC, allowing for more precise output voltages.+The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular order. The NetFPGA-SUME utilizes two Linear Technology LTC2974s to ensure that these sequencing requirements are met. Each LTC2974 supports "cascade sequence ON with time-based sequence off" and can monitor the input voltage, four output voltages, four output currents, and four external temperatures using a 16-bit ADC. Additionally, the LTC2974 can margin and trim up to four output voltages using a 10-bit DAC, allowing for more precise output voltages.
  
 {{ :sume:power_5.png?direct&600 |LTC2974 Sequencer and Supervisor}} {{ :sume:power_5.png?direct&600 |LTC2974 Sequencer and Supervisor}}
-//Figure 5. LTC2974 Sequencer and Supervisor.//+//Figure 6. LTC2974 Sequencer and Supervisor.//
  
-Figure 5 depicts the connections between the two LTC2974’s, as well as the signals that are used to control the power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts the LTC2974’s will perform a power on sequence when the power switch (SW1) is placed in the “ON” position. When a power on sequence is performed the rails come up in the following order:+Figure 6 depicts the connections between the two LTC2974s, as well as the signals that are used to control the power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts, the LTC2974s will perform a power on sequence when the power switch (SW1) is placed in the "ON" position. When a power on sequence is performed, the rails come up in the following order:
   - VCC1V0   - VCC1V0
   - VCC1V8   - VCC1V8
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   - MGTVAUX   - MGTVAUX
  
-When the input voltage falls below 9 volts, or the power switch transitions to the “OFF” position, the LTC2974’s perform a time-based off sequence and the rails come down in the following order:+When the input voltage falls below 9 volts, or the power switch transitions to the "OFF" position, the LTC2974s perform a time-based off sequence and the rails come down in the following order:
   - MGTVAUX   - MGTVAUX
   - VCC1V5, QDRVTT, and DDRVTT   - VCC1V5, QDRVTT, and DDRVTT
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 {{ :sume:power_6.png?direct&700 |Power ON/OFF Sequence}} {{ :sume:power_6.png?direct&700 |Power ON/OFF Sequence}}
-//Figure 6.Power ON/OFF Sequence.//+//Figure 7. Power ON/OFF Sequence.//
  
-The LTC2974’s constantly monitor the output voltage, current, and temperature associated with each channel (supply rail). This information, referred to as telemetry data, is used to determine the on status of each supply rail, as well as monitor for fault and warning conditions. When a fault or a warning occurs the FPGA application may be notified via an interrupt that’s signaled by the LTC2974’s ALERTB, AUXFAULTB, or FAULTB1 pins. The FPGA application may then read (using I2C) one or more of the LTC2974 status registers (defined in the datasheet) to determine the source of the fault or the warning. The output voltage, current, power, and temperature associated with any channel may also be read using the applicable PMBUS (I2C) commands, which are defined in the LTC2974 datasheet.+The LTC2974s constantly monitor the output voltage, current, and temperature associated with each channel (supply rail). This information, referred to as telemetry data, is used to determine the on status of each supply rail, as well as monitor for fault and warning conditions. When a fault or a warning occurs, the FPGA application may be notified via an interrupt that's signaled by the LTC2974’s ALERTB, AUXFAULTB, or FAULTB1 pins. The FPGA application may then read (using I2C) one or more of the LTC2974 status registers (defined in the datasheet) to determine the source of the fault or the warning. The output voltage, current, power, and temperature associated with any channel may also be read using the applicable PMBUS (I2C) commands, which are defined in the LTC2974 datasheet.
  
-In order to generate faults and warnings each channel of the LTC2974 must be configured with a nominal output voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault limit, and over temperature fault limit. Tables 2 and 3 describe the voltage and current limits as pre-configured by Digilent during the manufacturing process.+In order to generate faults and warnings, each channel of the LTC2974 must be configured with a nominal output voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault limit, and over temperature fault limit. Tables 2 & 3 describe the voltage and current limits as preconfigured by Digilent during the manufacturing process.
  
 ^ Supply Rail  ^ Under Voltage Fault Limit  ^ Under Voltage Warning Limit  ^ Nominal Voltage  ^ Overvoltage Warning Limit  ^ Overvoltage Fault Limit  ^ ^ Supply Rail  ^ Under Voltage Fault Limit  ^ Under Voltage Warning Limit  ^ Nominal Voltage  ^ Overvoltage Warning Limit  ^ Overvoltage Fault Limit  ^
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 //Table 2. Voltage fault and warning limits.// //Table 2. Voltage fault and warning limits.//
  
-//Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974’s.//+//Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.//
  
 ^ Supply Rail  ^ Undercurrent Fault Limit  ^ Rated Current  ^ Overcurrent Warning Limit  ^ Overcurrent Fault Limit  ^ ^ Supply Rail  ^ Undercurrent Fault Limit  ^ Rated Current  ^ Overcurrent Warning Limit  ^ Overcurrent Fault Limit  ^
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 //Table 3. Current fault and warning limits.// //Table 3. Current fault and warning limits.//
  
-//Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974’s.//+//Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.//
  
 === Fault and Warning Interrupt Sources === === Fault and Warning Interrupt Sources ===
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 When the LTC2974 detects a fault or a warning condition it may signal an interrupt by driving the ALERTB, AUXFAULTB, or FAULTB1 pins. When the LTC2974 detects a fault or a warning condition it may signal an interrupt by driving the ALERTB, AUXFAULTB, or FAULTB1 pins.
  
-The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs. The ALERTB pins of the two LTC2974’s (IC43 and IC44) are connected in a wire-and fashion via the PCON_ALERT_B net to pin J41 of the FPGA (IC12), as shown in Figure 7. Enabling the internal pull-up on pin J41 will allow the FPGA application to use this pin as an interrupt when any of the following situations occur:+The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs. The ALERTB pins of the two LTC2974s (IC43 and IC44) are connected in a wire-and fashion via the PCON_ALERT_B net to pin J41 of the FPGA (IC12), as shown in Fig. 7. Enabling the internal pull-up on pin J41 will allow the FPGA application to use this pin as an interrupt when any of the following situations occur:
   * Output overvoltage or under voltage fault/warning   * Output overvoltage or under voltage fault/warning
   * Output over current or under current fault/warning   * Output over current or under current fault/warning
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   * Channel output voltage has not reached or exceeded the under voltage fault limit set for that channel within TON_MAX_FAULT_LIMIT milliseconds (set to 15ms) of the output being enabled   * Channel output voltage has not reached or exceeded the under voltage fault limit set for that channel within TON_MAX_FAULT_LIMIT milliseconds (set to 15ms) of the output being enabled
  
-When any of the above faults occur the PCON_ALERT_B net will be driven low until the fault condition has been removed and the CLEAR_FAULTS command has been sent to both of the LTC2974’s (IC43 and IC44).+When any of the above faults occur the PCON_ALERT_B net will be driven low until the fault condition has been removed and the CLEAR_FAULTS command has been sent to both of the LTC2974s (IC43 and IC44).
  
 {{ :sume:power_7.png?direct&700 |ALERTB Interrupt Source}} {{ :sume:power_7.png?direct&700 |ALERTB Interrupt Source}}
-//Figure 7. ALERTB Interrupt Source.//+//Figure 8. ALERTB Interrupt Source.//
  
-The AUXFAULTB pins of the two LTC2974’s are connected in a wire-and fashion to the cathode of a Shottky diode via the AUXFAULT net as shown in Figure 8. The anode of the Shottky diode is connected to pin M41 on the FPGA via the PCON_AUXFAULT_B net and protects the FPGA pin from high voltages. The LTC2974’s are configured to drive the AUXFAULTB pin low when any of the follow conditions occur:+The AUXFAULTB pins of the two LTC2974s are connected in a wire-and fashion to the cathode of a Shottky diode via the AUXFAULT net as shown in Fig. 9. The anode of the Shottky diode is connected to pin M41 on the FPGA via the PCON_AUXFAULT_B net and protects the FPGA pin from high voltages. The LTC2974s are configured to drive the AUXFAULTB pin low when any of the follow conditions occur:
   * Output overvoltage fault on any channel   * Output overvoltage fault on any channel
   * Output over current or under current fault on any channel   * Output over current or under current fault on any channel
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 {{ :sume:power_8.png?direct&700 |AUXFAULTB Interrupt Source}} {{ :sume:power_8.png?direct&700 |AUXFAULTB Interrupt Source}}
-//Figure 8. AUXFAULTB Interrupt Source.//+//Figure 9. AUXFAULTB interrupt source.//
  
-The FAULTB1 pin of the LTC2974 is bi-directional open-drain input/output that can be configured to drive low in response to any channel entering a “faulted off state”. The LTC2974 can also be configured to disable any given channel in response to a logic low being detected on the FAULTB1 pin. However, it has been pre-configured by Digilent during manufacturing to serve strictly as an output that indicates when any channel has faulted off.+The FAULTB1 pin of the LTC2974 is bi-directional open-drain input/output that can be configured to drive low in response to any channel entering a "faulted off state". The LTC2974 can also be configured to disable any given channel in response to a logic low being detected on the FAULTB1 pin. However, it has been preconfigured by Digilent during manufacturing to serve strictly as an output that indicates when any channel has faulted off.
  
-The FAULTB1 pin of the two LTC2974’s are connected in a wire-and fashion to the gate of a transistor (N-FET). This transistor connects to the PCON_FAULT1 net, which is in turn connected to pin N40 of the FPGA as shown in Figure 9. When neither of the FAULTB1 pins is asserted low the gate of the transistor is pulled high and the PCON_FAULT1 net is connected to ground. When any channel enters the “faulted off state” the gate of the transistor is driven low and the transistor turns off. Enabling an internal pull-up on pin N40 will allow the FPGA application to detect logic ‘1’ when any channel has faulted off and logic ‘0’ when no channels have faulted off.+The FAULTB1 pin of the two LTC2974s are connected in a wire-and fashion to the gate of a transistor (N-FET). This transistor connects to the PCON_FAULT1 net, which is in turn connected to pin N40 of the FPGA, as shown in Fig. 10. When neither of the FAULTB1 pins is asserted low, the gate of the transistor is pulled high and the PCON_FAULT1 net is connected to ground. When any channel enters the "faulted off state," the gate of the transistor is driven low and the transistor turns off. Enabling an internal pull-up on pin N40 will allow the FPGA application to detect logic '1' when any channel has faulted off and logic '0' when no channels have faulted off.
  
 {{ :sume:power_9.png?direct&700 |FAULTB1 Interrupt Source}} {{ :sume:power_9.png?direct&700 |FAULTB1 Interrupt Source}}
-//Figure 9. FAULTB1 Interrupt Source.//+//Figure 10. FAULTB1 interrupt source.//
  
 === Power Consumption === === Power Consumption ===
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 %% %%
-Determining the input power consumption after taking into account the 10 Watt output power limitation of the FMC connector is difficult, as we do not know which supply rails will be utilized by an attached FMC mezzanine module. Assuming that all power was consumed from VADJ and 3P3V the total input power consumption would be reduced by+Determining the input power consumption after taking into account the 10 Watt output power limitation of the FMC connector is difficult, as we do not know which supply rails will be utilized by an attached FMC mezzanine module. Assuming that all power was consumed from VADJ and 3P3V, the total input power consumption would be reduced by
 12+((19.1-12)/0.9)=19.9 Watts. As a result, the input power consumption could be as high as 184.4-19.9=164.5 Watts when an FMC mezzanine module is attached. If no FMC mezzanine module is attached then the maximum input power consumption is 12+((19.1-12)/0.9)=19.9 Watts. As a result, the input power consumption could be as high as 184.4-19.9=164.5 Watts when an FMC mezzanine module is attached. If no FMC mezzanine module is attached then the maximum input power consumption is
 (40+22.5+(1.8*11)+(3.3*12)+8+3.6)/0.9+0.6=153.4 Watts. (40+22.5+(1.8*11)+(3.3*12)+8+3.6)/0.9+0.6=153.4 Watts.
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 After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of two ways: After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of two ways:
-  - A PC can use the Digilent USB-JTAG circuitry (port J16, labeled “PROG”) to program the FPGA any time the power is on.+  - A PC can use the Digilent USB-JTAG circuitry (port J16, labeled "PROG") to program the FPGA any time the power is on.
   - One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD.   - One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD.
  
 {{ :sume:sume_cfg.png?direct&700 | NetFPGA-SUME Configuration Options}} {{ :sume:sume_cfg.png?direct&700 | NetFPGA-SUME Configuration Options}}
  
-The figure above shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) selects between the two programming modes.+The figure above shows the different options available for configuring the FPGA. An on-board "mode" jumper (JP1) selects between the two programming modes.
  
 The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs).  The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs). 
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 A Virtex-7 690T bitstream is typically 229,878,496 bits and can take a long time to transfer. The time it takes to program the NetFPGA-SUME can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used. A Virtex-7 690T bitstream is typically 229,878,496 bits and can take a long time to transfer. The time it takes to program the NetFPGA-SUME can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools (ISE or Vivado) to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
  
-After being successfully programmed, the FPGA will cause the "DONE" LED to illuminate. Pressing the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from the parallel flash, assuming JP1 is not loaded.+After being successfully programmed, the FPGA will illuminate the "DONE" LED. Pressing the "PROG" button at any time will reset the configuration memory in the FPGA. After being reset, the FPGA will immediately attempt to reprogram itself from the parallel flash, assuming JP1 is not loaded.
  
 The following sections provide greater detail about programming the NetFPGA-SUME using the different methods available. The following sections provide greater detail about programming the NetFPGA-SUME using the different methods available.
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 Bitstreams are programmed into or read from flash using the dsumecfg tool included with the Adept Utilities package. You can also use this tool to set the BSS register. The Adept Utilities toolset can be downloaded for free from the Adept 2 page on the [[http://www.digilentinc.com|Digilent Website]]. Full documentation on the dsumecfg tool is included with the installation. The following should be kept in mind when using the dsumecfg tool: Bitstreams are programmed into or read from flash using the dsumecfg tool included with the Adept Utilities package. You can also use this tool to set the BSS register. The Adept Utilities toolset can be downloaded for free from the Adept 2 page on the [[http://www.digilentinc.com|Digilent Website]]. Full documentation on the dsumecfg tool is included with the installation. The following should be kept in mind when using the dsumecfg tool:
  
-  * In order to use dsumecfg you must have the NetFPGA-SUME connected to your computer via the USB-JTAG port.+  * In order to use dsumecfg, you must have the NetFPGA-SUME connected to your computer via the USB-JTAG port.
   *  To decrease programming times, we highly recommend enabling bitstream compression in Vivado or ISE when you generate your bitstream.   *  To decrease programming times, we highly recommend enabling bitstream compression in Vivado or ISE when you generate your bitstream.
   * dsumecfg will not work properly if an FMC card that inserts a JTAG device into the scan chain is attached to the NetFPGA-SUME.   * dsumecfg will not work properly if an FMC card that inserts a JTAG device into the scan chain is attached to the NetFPGA-SUME.
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 === DDR3 SODIMM === === DDR3 SODIMM ===
  
-The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), equivalent to 1700MT/s, due to the read margin issues. Please refer to Xilinx //Answer Record AR61853// for further information. The NetFPGA-SUME uses a VCC<sub>AUX-IO</sub> of 2.0V to support high performance DDR3 frequency settings. Please see //Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586)// and the micron //1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM// data sheet for more details. The DDR3 project in unit test project in netfpga repository provides a good starting point for project development.+The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM, which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), equivalent to 1700MT/s, due to the read margin issues. Please refer to Xilinx //Answer Record AR61853// for further information. The NetFPGA-SUME uses a VCC<sub>AUX-IO</sub> of 2.0V to support high performance DDR3 frequency settings. Please see //Xilinx 7-Series FPGAs Memory Interface Solutions User Guide (UG586)// and the micron //1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM// data sheet for more details. The DDR3 project in unit test project in netfpga repository provides a good starting point for project development.
  
-=== QDR II+ SRAM ===+=== QDRII+ SRAM === 
 + 
 +Three Cypress CY7C25652KV18 Quad Data Rate II+ (QDRII+) SRAMs are provided for applications that require high speed, low latency memory. Each component provides a 36 bit wide data bus and has a density of 72 Megabits. Common applications include FIFO buffers and look-up tables. The notion of "Quad" data rate comes from the ability to simultaneously read from a unidirectional read port and write to a unidirectional write port on both clock edges. The QDRII+ SRAMs on NetFPGA-SUME board are capable of operating at up to 500MHz to yield data transfer rates of up to 1GT/s per 36-bit wide data bus. The Xilinx Memory Interface Generator (MIG) is able to generate and configure an native interface into the QDRII+ via the user friendly wizard tool. More information regarding the QDRII+ memory part and the Xilinx MIG tool can be found in the Cypress //CY7C25632KV18/CY7C25652KV18 
 +// data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7-Series FPGAs Memory Interface Solutions User Guide (UG586)//.  
 + 
 +QDRA and QDRB share FPGA bank 17, which means that in order to access them simultaneously, a bank sharing solution must be used that extends beyond the default functionality of the MIG. This solution is still currently being developed. Please refer to //Xilinx Answer Record 41706// for further information.
  
-Three 72Mbits Cypress CY7C25652KV18 QDRII+ Quad Data Rate SRAMs are provided for applications that require high speed, low latency memory. Common applications include FIFO buffers and look-up tables. The notion of “Quad” data rate comes from the ability to simultaneously read from a unidirectional read port and write to a unidirectional write port on both clock edges. The QDRII+ SRAMs on NetFPGA-SUME board are capable of operating at up to 500MHz to yield data transfer rates of up to 1GT/s per 36-bit wide data bus. The Xilinx Memory Interface Generator (MIG) is able to generate and configure an native interface into the QDRII+ via the user friendly wizard tool. More information regarding the QDRII+ memory part and the Xilinx MIG tool can be found in the Cypress //CY7C25632KV18/CY7C25652KV18 
-// data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586)//. As QDRA and QDRB shares FPGA bank 17, a bank sharing solution for QDRA and QDRB working simultaneously is still in development. Please refer to //Xilinx Answer Record 41706// for further information. 
 ==== Storage ==== ==== Storage ====
  
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 flash and configuring the FPGA from stored bitstreams, see the section titled "Configuration using Parallel Flash". flash and configuring the FPGA from stored bitstreams, see the section titled "Configuration using Parallel Flash".
  
-=== Micro-SD Card ===+=== MicroSD Card === 
 + 
 +The microSD card connector on NetFPGA-SUME board provides a removable non-volatile storage resource. This connector supports a microSD memory card and meets all physical layer requirements of both SPI and SD bus protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at 3.3V to support SC, HC, and XC class SD cards. Please see SD Specifications Part 1 Physical Layer Simplified Specification by the Technical Committee of the SD Card Association for more details regarding the use of SD memory cards with this connector.
  
-The micro-SD card connector on NetFPGA-SUME board provides a removable non-volatile storage resource. This connector supports a micro-SD memory card and meets all physical layer requirements of both SPI and SD bus protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at 3.3V to support SC, HC, and XC class SD cards. Please see SD Specifications Part 1 Physical Layer Simplified Specification by the Technical Committee of the SD Card Association for more details regarding the use of SD memory cards with this connector. 
 ==== SATA ==== ==== SATA ====
  
-The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7 Series FPGAs Transceivers Wizard v2.6 User Guide// for more information.+The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7-Series FPGAs Transceivers Wizard v2.6 User Guide// for more information.
 ==== PCI Express ==== ==== PCI Express ====
  
-The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA’s high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx 7 Series FPGAs Integrated Block for PCI Express V2.0 (PG054) product guide and 7 Series FPGAs GTX/GTH Transceivers (UG476) user guide for more information.+The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA's high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx //7-Series FPGAs Integrated Block for PCI Express V2.0// (PG054) product guide and //7-Series FPGAs GTX/GTH Transceivers// (UG476) user guide for more information.
  
  
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 Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard for  Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard for 
-additional detail regarding standard FMC module and carrier requirements. Refer to Appendix B for specific I/O  +additional details regarding standard FMC module and carrier requirements. Refer to Appendix B of this document for specific I/O constraints relating FPGA pins to their associated FMC control and connector pins.
-constraints relating FPGA pins to their associated FMC control and connector pins.+
  
 === QTH === === QTH ===
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 === Pmod === === Pmod ===
  
-{{ :basys3-pmod_connector.png?400 |Pmod Connector}}+{{ :basys3-pmod_connector.png?400 |Pmod Port}}
  
-The NetFPGA-SUME board also provides a Pmod Connector for peripheral extension. The Pmod connectors are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching.+The NetFPGA-SUME board also provides a Pmod port for peripheral extension. The Pmod port is arranged as a 2x6 vertical, 100-mil female connector that mates with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown above. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching.
  
-Please note that the signals on Pmod connector is connected to FPGA via two 4-bit dual-supply bus transceivers (IC1/2 SN74AVC4T774) with configurable voltage translation and 3-state outputs. You need to specifically set DIR for each pins to control the signal direction. The bus transceiver is enabled by driving OE pin of the bus transceiver low.+The signals on the Pmod port are connected to the FPGA via two 4-bit dual-supply bus transceivers (IC1 and IC2, part number SN74AVC4T774) with configurable voltage translation and 3-state outputs. You need to specifically set DIR for each pin to control the signal direction. The bus transceiver is enabled by driving OE pin of the bus transceiver low.
 ==== Basic I/O ==== ==== Basic I/O ====
  
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 The two LEDs are green and are illuminated when driven high. It is possible to control the brightness by providing a pulse width modulated signal that varies the duty cycle from 0% to 100%. The two LEDs are green and are illuminated when driven high. It is possible to control the brightness by providing a pulse width modulated signal that varies the duty cycle from 0% to 100%.
  
-An additional pushbutton (BTN3) is attached to the PROGRAM_B pin of the Virtex-7 FPGA. Pressing this button will clear the configuration inside the FPGA and cause the DONE pin to go low. If the mode jumper is not shorted, this will also trigger the CPLD to reprogram the FPGA with a bitstream stored in flash (See the "FPGA Configuration" section for more info).+An additional red pushbutton (BTN3, labeled PROG) is attached to the PROGRAM_B pin of the Virtex-7 FPGA. Pressing this button will clear the configuration inside the FPGA and cause the DONE pin to go low. If the mode jumper is not shorted, this will also trigger the CPLD to reprogram the FPGA with a bitstream stored in flash (See the "FPGA Configuration" section for more info).
  
 LD4 is attached to the DONE pin of the FPGA, and is illuminated whenever the FPGA is configured with a valid bitstream. LD4 is attached to the DONE pin of the FPGA, and is illuminated whenever the FPGA is configured with a valid bitstream.