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reference:instrumentation:analog-discovery-pro:reference-manual [2020/01/13 17:11] – [Pinout Diagram] Mircea Dabacan | reference:instrumentation:analog-discovery-pro:reference-manual [2021/01/21 17:26] (current) – removed Arthur Brown | ||
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- | ====== Analog Discovery PRO Reference Manual ====== | ||
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- | The Digilent Analog Discovery PRO™, is a multi-function instrument that allows users to measure, visualize, generate, record, and control mixed signal circuits of all kinds. The Analog Discovery PRO is powerful enough to replace a stack of lab equipment, providing engineering students, hobbyists, and electronics enthusiasts the freedom to work with analog and digital circuits in virtually any environment, | ||
- | FIXME | ||
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- | == Download This Reference Manual == | ||
- | * {{ : | ||
- | |||
- | ===== Features ===== | ||
- | |||
- | The analog and digital inputs and outputs can be connected to a circuit using BNC probes. Driven by the free WaveForms software, the Analog Discovery PRO can be configured to work as any one of several traditional instruments, | ||
- | |||
- | * Four-channel oscilloscope (1MΩ, ±25V, differential, | ||
- | * Two-channel arbitrary function generator (±5V, 14-bit, 100MS/s, FIXME! | ||
- | * 16-channel digital logic analyzer (1V...3.3V CMOS, 100MS/ | ||
- | * 16-channel pattern generator (1V...3.3V CMOS, 100MS/ | ||
- | * 16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic training applications ((These 16 digital lines are shared by the Logic Analyzer, Pattern Generator and Digital I/O. They are always inputs, some of them can be set to be outputs also. Digital I/O has precedence in case of output conflict with the Pattern Generator.)) | ||
- | * Two input/ | ||
- | * VIO programmable power supply (1V…3.3V). The value of VIO defines the logic compatibility of the digital pins. Low power circuit under test can be supplied by VIO. | ||
- | * Four-channel voltmeter (share scope inputs) (AC, DC, ±25V) | ||
- | * Network analyzer – Bode, Nyquist, Nichols transfer diagrams of a circuit. Range: 1Hz to 10MHz | ||
- | * Spectrum Analyzer – power spectrum and spectral measurements (noise floor, SFDR, SNR, THD, etc.) | ||
- | * Digital Bus Analyzers (SPI, I²C, UART, Parallel, CAN) | ||
- | |||
- | |||
- | The Analog Discovery PRO was designed for FIXME! Marketing FIXME!. Its features and specifications, | ||
- | |||
- | |||
- | Analog Discovery PRO is the high performance version | ||
- | * Four single ended scope inputs (compared to two differential scope inputs) | ||
- | * Higher scope input circuitry bandwidth: 60MHz+ (compared to 30MHz+). | ||
- | * Higher AWG output circuitry bandwidth: FIXME! (compared to 12MHz+). | ||
- | * Improved signal/ | ||
- | * Variable VIO for flexible logic compatibility of the digital input/ | ||
- | |||
- | ==== Pinout Diagram ==== | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | |||
- | {{ : | ||
- | |||
- | // | ||
- | ===== 1.1 Architectural Overview and Block Diagram ===== | ||
- | |||
- | Analog Discovery 2's high-level block diagram is presented in [[analog_discovery_2: | ||
- | |||
- | |||
- | Signals in the **Analog Input** block, also called the **Scope**, use " | ||
- | |||
- | * The** Analog Inputs/ | ||
- | * **Input Divider and Gain Control**: high bandwidth input adapter/ | ||
- | * **Buffer**: high impedance buffer | ||
- | * **Driver**: provides appropriate signal levels and protection to the ADC. Offset voltage is added for vertical position setting | ||
- | * **Scope Reference and Offset**: generates and buffers reference and offset voltages for the scope stages | ||
- | * **ADC**: the analog-to-digital converter for both scope channels. | ||
- | * The **Arbitrary Outputs/ | ||
- | * **DAC**: the digital-to-analog converter for both AWG channels | ||
- | * **I/V**: current to bipolar voltage converters | ||
- | * **Out**: output stages | ||
- | * **Audio**: audio amplifiers for headphone | ||
- | * A precision **Oscillator** and a **Clock Generator** provide a high quality clock signal for the AD and DA converters. | ||
- | * The **Digital I/O** block exposes protected access to the FPGA pins assigned for the Digital Pattern Generator and Logic Analyzer. | ||
- | * The **Power Supplies and Control** block generates all internal supply voltages as well as user supply programmable voltages. The control block also monitors the device power consumption for USB compliance when power is supplied via the USB connection. When external power supply is used, the control block allows more power for the user supplies. Under the FPGA control, power for unused functional blocks can be turned off. | ||
- | * The **USB Controller** interfaces with the PC for programming the volatile FPGA memory after power on or when a new configuration is requested. After that, it performs the data transfer between the PC and FPGA. | ||
- | * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Analog Discovery 2 includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The WaveForms software uses these parameters to correct the acquired data and the generated signals | ||
- | |||
- | |||
- | In the sections that follow, schematics are not shown separately for identical blocks. | ||
- | |||
- | {{ : | ||
- | |||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | ====== 2. Scope ====== | ||
- | |||
- | // | ||
- | |||
- | For those applications which scope GND cannot be the USB ground, a USB isolation solution, such as what is described in ADI’s [[http:// | ||
- | ===== 2.1. Scope Input Divider and Gain Selection ===== | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | Two symmetrical R-C dividers provide: | ||
- | * Scope input impedance = 1MOhm || 24pF | ||
- | * Two different attenuations for high-gain/ | ||
- | * Controlled capacitance, | ||
- | * Constant attenuation and high CMMR over a large frequency range (trimmer adjusted) | ||
- | * Protection for overvoltage (with the ESD diodes of the ADG612 inputs) | ||
- | |||
- | The maximum voltage rating for scope inputs is limited by C1 thru C24 to: | ||
- | |||
- | $$-50V< | ||
- | |||
- | The maximum swing of the input signal to avoid signal distortion by opening the ADG612 ESD diodes is (for both low-gain and high-gain): | ||
- | |||
- | $$-26V< | ||
- | |||
- | An analog switch ([[http:// | ||
- | |||
- | The ADG612 quad switch was used because it provides excellent impedance and bandwidth parameters: | ||
- | * 1 pC charge injection | ||
- | * ±2.7 V to ±5.5 V dual-supply operation | ||
- | * 100 pA maximum at 25°C leakage currents | ||
- | * 85 Ω on resistance | ||
- | * Rail-to-rail switching operation | ||
- | * Typical power consumption: | ||
- | * TTL-/ | ||
- | * -3 dB Bandwidth 680 MHz | ||
- | * 5 pF each of CS, CD (ON or OFF) | ||
- | |||
- | The low gain is: $$\frac {V_{mux}}{V_{in}}=\frac {R_6}{R_1+R_4+R_6}=0.019\label{3}\tag{3}$$ | ||
- | |||
- | The low gain is used for input voltages: $$| V_{indiff} | = | V_{inP}-V_{inN} |< | ||
- | |||
- | The high gain is: $$\frac {V_{mux}}{V_{in}} = \frac {R_4 + R_6}{R_1 + R_4 + R_6} = 0.212 \label{5}\tag{5}$$ | ||
- | |||
- | The high gain is used for input voltages: $$|V_{indiff}| = |V_{inP} - V_{inN}|< | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | |||
- | ===== 2.2. Scope Buffer ===== | ||
- | |||
- | A non-inverting OpAmp stage provides very high impedance as load for the input divider [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The useful features of the [[http:// | ||
- | * FET input amplifier | ||
- | * 1 pA input bias current | ||
- | * Low cost | ||
- | * High speed: 145 MHz, −3 dB bandwidth (G = +1) | ||
- | * 180 V/μs slew rate (G = +2) | ||
- | * Low noise 7 nV/√Hz (f = 10 kHz), 0.6 fA/√Hz (f = 10 kHz) | ||
- | * Wide supply voltage range: 5 V to 24 V | ||
- | * Rail-to-rail output | ||
- | * Low offset voltage 1.5 mV maximum | ||
- | * Excellent distortion specifications | ||
- | * SFDR −88 dBc @ 1 MHz | ||
- | * Low power: 6.4 mA/ | ||
- | * Small packaging: MSOP-8 | ||
- | |||
- | |||
- | Resistors and capacitors in the figure help to maximize the bandwidth and reduce peaking (which might be significant at unity gain). | ||
- | |||
- | The [[http:// | ||
- | |||
- | The maximum input voltage swing is: $-5.5V< | ||
- | |||
- | The maximum output voltage swing is: $-5.38V< | ||
- | |||
- | The gain is: $$\frac {V_{buf}}{V_{mux}}=1\label{9}\tag{9}$$ | ||
- | |||
- | ===== 2.3. Scope Reference and Offset ===== | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | |||
- | |||
- | [[http:// | ||
- | * Initial accuracy: ±0.1% (maximum) | ||
- | * Low temperature coefficient: | ||
- | * Low quiescent current: 100 μA (maximum) | ||
- | * Output noise (0.1 Hz to 10 Hz): <10 μV p-p at 1.2 V (typical) | ||
- | |||
- | |||
- | [[http:// | ||
- | * Low power, smallest dual nanoDAC | ||
- | * 2.7 V to 5.5 V power supply | ||
- | * Serial interface up to 50 MHz | ||
- | |||
- | |||
- | [[http:// | ||
- | * Very low supply current: 13 μA typical | ||
- | * Low offset voltage: 15 μV maximum | ||
- | * Offset voltage drift: 20 nV/ | ||
- | * High PSRR: 110 dB minimum | ||
- | * Rail-to-rail input/ | ||
- | * Unity-gain stable | ||
- | |||
- | The reference voltages generated for the scope stages are: | ||
- | $$V_{refSC}=V_{ref1V2}\cdot \left( 1+ \frac {R_{79}}{R_{80}} \right) =2V \label{10}\tag{10}$$ | ||
- | |||
- | The offset voltages for the scope stages are: | ||
- | $$0 \le V_{offSC} = V_{outAD5643} \cdot \left( 1+ \frac {R_{77}}{R_{78}} \right) < 4.044V \label{11}\tag{11}$$ | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | ===== 2.4. Scope Driver ===== | ||
- | |||
- | |||
- | |||
- | [[http:// | ||
- | * Small signal bandwidth: 260 MHz | ||
- | * Extremely low harmonic distortion: -122 dB THD at 50 kHz, -96 dB THD at 1 MHz | ||
- | * Low input voltage noise: 3.9 nV/√Hz | ||
- | * 0.35 mV maximum offset voltage | ||
- | * Settling time to 0.1%: 34 ns | ||
- | * Rail-to-rail output | ||
- | * Adjustable output common-mode voltage | ||
- | * Flexible power supplies: 3 V to 7 V(LFCSP) | ||
- | * Ultra-low power: 1.25mA | ||
- | |||
- | |||
- | IC2 [[analog_discovery_2: | ||
- | * Driving the differential inputs of the ADC (with low impedance outputs) | ||
- | * Providing the common mode voltage for the ADC | ||
- | * Adding the offset (for vertical position on the scope). VREF_SC1 is constant at midrange of VOFF_SC1. This way, the added offset can be either positive or negative. | ||
- | * ADC protection by clamping the output signals. Protection is important since IC2 is supplied ±3.3V, while the ADC inputs only support -0.1…2.1V. The IC2A constant output signals act as clamping voltages for the Schottky diodes D1, D2. | ||
- | |||
- | {{ : | ||
- | |||
- | // | ||
- | |||
- | |||
- | [[http:// | ||
- | |||
- | $$-3.5V< | ||
- | |||
- | The signal gain is: | ||
- | |||
- | $$\frac{V_{ADCdiff}}{V_{bufdiff}}=\frac{R_9}{R_8}=\frac{R_{17}}{R_{16}}=1.77\label{13}\tag{13}$$ | ||
- | |||
- | The offset gain is: | ||
- | |||
- | $$\frac {V_{ADCdiff}}{V_{offSC} - V_{refSC}} = \frac {R_9}{R_3} = \frac {R_{17}}{R_{22}} = 1 \label{14}\tag{14}$$ | ||
- | |||
- | The common mode gain is: | ||
- | |||
- | $$\dfrac{V_{CM}}{V_{ADCP}+V_{ADCN}/ | ||
- | |||
- | The clamping voltages are: | ||
- | |||
- | $$V_{Out-IC2A}=V_{CM}-\frac{AVCC1V8}{2}\cdot\frac{R_{23}}{R_{25}} = 0.9V-\frac{1.8V}{2}\cdot\frac{4.99K}{6.34K}=0.2V\label{16}\tag{16}$$ | ||
- | |||
- | $$V_{Out+IC2A}=V_{CM}-\frac{AVCC1V8}{2}\cdot\frac{R_{23}}{R_{25}} = 0.9V+\frac{1.8V}{2}\cdot\frac{4.99K}{6.34K}=1.6V\label{17}\tag{17}$$ | ||
- | |||
- | D1, D2 clamp the VADC signals to the protected levels of: | ||
- | |||
- | $$-0.1V< | ||
- | |||
- | ---- | ||
- | ===== 2.5. Clock Generator ===== | ||
- | |||
- | A precision oscillator (IC31) generates a low jitter, 20 MHz clock (see [[analog_discovery_2: | ||
- | |||
- | The ADF4360-9 Clock Generator PLL with Integrated VCO is configured for generating a 200 MHz differential clock for the ADC and a 100 MHz single-ended clock for the DAC. | ||
- | |||
- | Analog Devices ADIsimPLL software was used for designing the clock generator (see [[analog_discovery_2: | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | |||
- | ===== 2.6. Scope ADC ===== | ||
- | |||
- | |||
- | |||
- | ==== 2.6.1. Analog Section ==== | ||
- | |||
- | The Analog Discovery 2 uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC (Analog part number [[http:// | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The important features of AD9648: | ||
- | * SNR = 74.5dBFS @70 MHz | ||
- | * SFDR =91dBc @70 MHz | ||
- | * Low power: 78mW/ | ||
- | * Differential analog input with 650 MHz bandwidth | ||
- | * IF sampling frequencies to 200 MHz | ||
- | * On-chip voltage reference and sample-and-hold circuit | ||
- | * 2 V p-p differential analog input | ||
- | * DNL = ±0.35 LSB | ||
- | * Serial port control options | ||
- | * Offset binary, gray code, or two's complement data format | ||
- | * Optional clock duty cycle stabilizer | ||
- | * Integer 1-to-8 input clock divider | ||
- | * Data output multiplex option | ||
- | * Built-in selectable digital test pattern generation | ||
- | * Energy-saving power-down modes | ||
- | * Data clock out with programmable clock and data alignment | ||
- | |||
- | The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | ||
- | |||
- | The differential input voltage range is: | ||
- | |||
- | $$-1V< | ||
- | |||
- | |||
- | ==== 2.6.2. Digital Section ==== | ||
- | |||
- | |||
- | The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V. | ||
- | |||
- | To minimize the number of used FPGA pins; a multiplexed mode is used, to combine the two channels on a single data bus. CLKOUT_SC is provided to the FPGA for synchronizing data (see [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | |||
- | ---- | ||
- | |||
- | ===== 2.7. Scope Signal Scaling ===== | ||
- | |||
- | |||
- | Combining Gain equations \ref{3}, \ref{5}, \ref{9}, \ref{13}, \ref{14}, and \ref{15} from previous chapters, the total scope gains are: | ||
- | |||
- | $$Low \; gain = \frac{V_{ADC\; | ||
- | $$High \; gain = \frac{V_{ADC\; | ||
- | |||
- | Combining the ADC input voltage range shown in \ref{19} with $V_{offSC}$ at the midrange of \ref{11} (scope vertical position at 0), the Vin range is: | ||
- | |||
- | $$at \; low \; gain: -30V< | ||
- | $$at \; high \; gain: -2.7V< | ||
- | |||
- | To cover component value tolerances and to allow software calibration, | ||
- | |||
- | $$at \; low \; gain: -25V< | ||
- | $$at \; high \; gain: -2.5V< | ||
- | |||
- | With the 14-bit ADC, the absolute resolution of the scope is: | ||
- | |||
- | $$at \; low \; gain: \frac{58.6V}{2^{14}}=3.58mV$$ | ||
- | $$at \; high \; gain: \frac{5.3V}{2^{14}}=0.32mV\label{23}\tag{23}$$ | ||
- | |||
- | The effect of the offset setting (scope vertical position) can be calculated from \ref{10}, \ref{11} and \ref{14}: | ||
- | |||
- | $$-2V< | ||
- | |||
- | The vertical position setting moves the signals vertically on the scope screen (relative to vertical screen center) by $V_{off eq in}$: | ||
- | |||
- | $$at \; low \; gain: -59.3V< | ||
- | $$at \; high \; gain: -5.39V< | ||
- | |||
- | The above adds an equivalent offset voltage $V_{off eq in}$ to $V_{in diff}$, translating the ranges in \ref{21} and \ref{22} by $V_{off eq in}$ , up to the limits in \ref{25}. | ||
- | |||
- | Equations \ref{2}, \ref{7}, \ref{8}, \ref{12}, and \ref{19} show signal range boundaries for keeping ICs in the input/ | ||
- | |||
- | To be visible on the scope screen and not distorted, a signal should be included in all the solid line polygons of a figure (**linear range** = geometrical intersection of the surfaces). | ||
- | |||
- | Only the differential input voltage is shown on the scope screen. The common mode voltage information is removed by the differential structure of the Analog Discovery 2 scope. A signal overpassing the linear range will be distorted on the scope screen, i.e. the graphical representation will be clamped. In the diagrams below, a signal outside the linear range will be clamped to the closest point in the linear range. The clamping point is not necessarily at the scope screen top or bottom edge, as explained below. | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The dashed rectangles represent the display area on the scope screen. There are three dashed rectangles in each diagram: the middle one corresponds to the vertical position set to 0 (VoffSc = 2.022V in equation \ref{11}. The left one shows the display area when vertical position is set to maximum (VoffSc = 4.044V), and the right one corresponds to the minimum (negative) vertical position (VoffSc = 0V). Any intermediate vertical position is possible, moving the displayable area (virtual dashed rectangle) to any intermediate position. A signal crossing the long side of the dashed rectangle exceeds the displayable input voltage range causing the ADC to saturate (either at zero or at Full Scale). This is represented on the scope screen with dashed line warning to the user. | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | A signal keeping within the dashed rectangle but crossing any solid line overrides electrical limits of intermediate circuits in the signal path (see the legend of the figures). This results in distorting the signal without saturating the ADC. The software has no information about this situation and cannot warn the user with specific signal representation. It is the user’s responsibility to understand and avoid such situations. | ||
- | |||
- | For low gain [[analog_discovery_2: | ||
- | |||
- | For high gain [[analog_discovery_2: | ||
- | |||
- | $$-26V< | ||
- | |||
- | Additionally, | ||
- | |||
- | $$-7.5V< | ||
- | |||
- | Note the difference between typical parameter values considered by the figures and the safer min/max values used for the equations. | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | ===== 2.8 Scope Spectral Characteristics ===== | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | The Network Analyzer was used, the WaveGen was set to External, the Gain was set at x10 (high-gain) for the upper figure, and x0.1 (low-gain) for the lower one. For both scales, the 3dB bandwidth is 30 MHz+. The 0.5dB bandwidth is 10 MHz and the 0.1dB bandwidth is 5 MHz. | ||
- | |||
- | The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The Analog Discovery 2 exhibits 10 MHz @ 0.5dB, meaning that a 10 MHz sinusoidal signal is shown with a flatness error of a max 5.6%. 5 MHz @ 1dB means that a 5 MHz sinusoidal signal is shown with a flatness error of a max 1.5%. | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | As shown above, the measurements in Fig. 14 were taken with a coax cable and a Digilent Discovery BNC adapter. This is the optimal setup that allows maximal Analog Discovery spectral performance. The wire kit included with the Analog Discovery 2 is a cheap, easy-to-use probing solution. However, the wire kit reduces the bandwidth of the scope and is susceptible to inducing noise and crosstalk from adjacent circuits. [[analog_discovery_2: | ||
- | |||
- | ---- | ||
- | ====== 3. Arbitrary Waveform Generator ====== | ||
- | |||
- | ===== 3.1. AWG DAC ===== | ||
- | |||
- | The Analog Devices [[http:// | ||
- | * Power dissipation @ 3.3V, 2 mA output: 86 mW @ 125MS/s, sleep mode: <3 mW @ 3.3V | ||
- | * Supply voltage: 1.8V to 3.3V | ||
- | * SFDR to Nyquist: 84 dBc @ 1 MHz output, 75 dBc @ 10 MHz output | ||
- | * AD9717 NSD @ 1 MHz output, 125MS/s, 2 mA: −151 dBc/ | ||
- | * Differential current outputs: 1 mA to 4 mA | ||
- | * CMOS inputs with single-port operation | ||
- | * Output common mode: 0 to 1.2 V | ||
- | * Small footprint, 40-lead LFCSP RoHS-compliant package | ||
- | |||
- | The parallel Data Bus and the SPI configuration bus are driven by the FPGA. | ||
- | The single ended 100 MHz clock is provided by the clock generator. | ||
- | External Vref1V_AWG reference voltage is used. | ||
- | The output currents (Iout_AWGx_P and _N) are converted to voltages in the I/V stage. | ||
- | The Full Scale is set via the FSADJx pins [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The [[http:// | ||
- | * −3 dB bandwidth, 150 MHz | ||
- | * Single-supply 1.8V to 5.5V operation | ||
- | * Low on resistance: 2.5 Ω typical | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | ===== 3.2. AWG Reference and Offset ===== | ||
- | |||
- | |||
- | As shown in [[analog_discovery_2: | ||
- | |||
- | $$V_{ref1V\_AWG}=V_{ref1V2\_AWG} \cdot \frac{R_{41}}{R_{39}+{R_{41}}}=1V\label{28}\tag{28}$$ | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | Buffered versions are provided to the I/V stages and individually for each AWG channel to minimize crosstalk. | ||
- | |||
- | The Full Scale DAC output current is: | ||
- | |||
- | $$I_{outAWGFS}=32 \cdot \frac{V_{ref1V\_AWG}}{R_{set}}\label{29}\tag{29}$$ | ||
- | |||
- | For high-gain: | ||
- | |||
- | $$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{8k \Omega}=4mA\label{30}\tag{30}$$ | ||
- | |||
- | |||
- | For low-gain: | ||
- | |||
- | $$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{32k \Omega}=1mA\label{31}\tag{31}$$ | ||
- | |||
- | An [[http:// | ||
- | |||
- | * Low power, smallest quad 14-bit nanoDAC | ||
- | * 2.7 V to 5.5 V power supply | ||
- | * Monotonic by design | ||
- | * Power-on reset to zero scale/ | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The Full Scale voltage of all IC43 outputs is: | ||
- | |||
- | $$V_{offAWGFS}=V_{SET\_USRFS}=V_{ref1V2AWG}=1.2V\label{32}\tag{32}$$ | ||
- | |||
- | ---- | ||
- | ===== 3.3. AWG I/V ===== | ||
- | |||
- | IC 15 in [[analog_discovery_2: | ||
- | |||
- | Important [[http:// | ||
- | * Low cost | ||
- | * 325 MHz, −3 dB bandwidth (G = +1) | ||
- | * 1000 V/μs slew rate | ||
- | * Gain flatness: 0.1 dB to 28 MHz | ||
- | * Low noise: 7 nV/√Hz | ||
- | * Low power: 5.4 mA/ | ||
- | * Low distortion: −85 dBc@5MHz, RL=1kΩ | ||
- | * Wide supply range from 3 V to 12 V | ||
- | * Small packaging | ||
- | |||
- | $$V_{Audio}=I_{outAWGP} \cdot R_{148}-I_{outAWGN} \cdot R_{142}=$$ | ||
- | $$=( 1-2 \cdot \{ A_U \} ) \cdot I_{outAWGFS} \cdot R_{142}=\{ A_b \} \cdot I_{outAWGFS} \cdot R_{142}\label{33}\tag{33}$$ | ||
- | |||
- | |||
- | Where: | ||
- | |||
- | $$\left\{ {{A_U}} \right\} = \frac{D}{{{2^N}}} \in \left[ {\left. {0 \ldots 1} \right)} \right.;\; - \; | ||
- | |||
- | $$\left\{ {{A_B}} \right\} = \left( {1 - 2 \cdot \left\{ {{A_U}} \right\}} \right) \in \left[ {\left. { - 1 \ldots 1} \right)} \right.;\; - \; | ||
- | |||
- | $$D \in \left[ {\left. {0 \ldots {2^{14}}} \right)} \right. = \left[ {0 \ldots {2^{14}} - 1} \right];\; - \; | ||
- | |||
- | |||
- | The Voltage range extends between: | ||
- | |||
- | $$ - V_{AudioFS} \le V_{Audio} < - V_{AudioFS}\label{35}\tag{35}$$ | ||
- | |||
- | Where (for high gain, respectively, | ||
- | |||
- | $$V_{AudioFS\; | ||
- | $$V_{AudioFS\; | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | ---- | ||
- | |||
- | ===== 3.4. AWG Out ===== | ||
- | |||
- | IC16 in [[analog_discovery_2: | ||
- | |||
- | * FET input: 0.6 pA input bias current | ||
- | * Stable for gains ≥8 for High-Capacitive Load | ||
- | * High speed: 54 MHz@−3 dB (G = +10) | ||
- | * 640 V/µs slew rate | ||
- | * Low noise:6.6 nV/√Hz; 0.6 fA/ | ||
- | * Low offset voltage (1.0 mV max) | ||
- | * Rail-to-rail output | ||
- | * Low distortion: SFDR 95 dBc @ 1 MHz | ||
- | * Low power: 6.5 mA typical supply current | ||
- | * Low cost; Small packaging: SOT-23-5 | ||
- | |||
- | Matching the impedances in the inverting and non-inverting inputs of IC16: | ||
- | |||
- | $$\frac{1}{{{{\mathbf{R}}_{140}}}} + \frac{1}{{{{\mathbf{R}}_{141}}}} + \frac{1}{{{{\mathbf{R}}_{144}}}} = \frac{1}{{{{\mathbf{R}}_{147}}}} + \frac{1}{{{{\mathbf{R}}_{149}}}}\label{37}\tag{37}$$ | ||
- | |||
- | $$V_{outAWG}=-V_{Audio} \cdot \frac{R_{141}}{R_{144}}+\left(2 \cdot V_{offAWG}-V_{ref1V2AWG}\right) \cdot \frac{R_{141}}{R_{140}}\label{38}\tag{38}$$ | ||
- | |||
- | The first term in equation \ref{38} represents the actual wave amplitude, with a range of: | ||
- | |||
- | $$ - 5.45V < - 5V < V_{ACoutAWG\; | ||
- | $$ - 1.36V < 1.25V < V_{ACoutAWG\; | ||
- | |||
- | |||
- | Low-gain is used to generate low amplitude signals with improved accuracy. Any amplitude of the output signal is derivable by combining LowGain/ | ||
- | |||
- | With the 14-bit DAC, the absolute resolution of the AWG AC component is: | ||
- | |||
- | $$at\; | ||
- | $$at\; | ||
- | |||
- | The second term in equation \ref{38} shows the DC component (AWG offset), with a range of (for either LowGain or HighGain): | ||
- | |||
- | $$ - 5.5V < 5V < V_{DCoutAWG} < 5V < 5.5V\label{41}\tag{41}$$ | ||
- | |||
- | AD8067 is supplied with $\pm 5.5V$; to avoid saturation the user should keep the sum of AC and DC components in \ref{38} to: | ||
- | |||
- | $$ - 5.5V < 5V < V_{outAWG} < 5V < 5.5V\label{42}\tag{42}$$ | ||
- | |||
- | Only **bolded** ranges are used in equations \ref{39}, \ref{41}, and \ref{42}, for providing tolerance margins. | ||
- | |||
- | The R145 PTC thermistor provides thermal protection in case of an output shortcut. | ||
- | |||
- | |||
- | ---- | ||
- | |||
- | ===== 3.5. Audio ===== | ||
- | |||
- | A stereo audio output combines the two AWG channels [[analog_discovery_2: | ||
- | |||
- | * Single-supply operation: 2.5 V to 6 V | ||
- | * High output current: ±250 mA | ||
- | * Low shutdown supply current: 100 nA | ||
- | * Low supply current: 750 μA/ | ||
- | * Very low input bias current | ||
- | |||
- | A single 3.3V supply is used. | ||
- | |||
- | $$V_{outIC18}=-2 \cdot V_{Audio}+1.5V\label{43}\tag{43}$$ | ||
- | |||
- | The first term in equation \ref{43} is the audio signal. The second term is the common mode DC component, removed by AC coupling. | ||
- | |||
- | The audio signal range is: | ||
- | |||
- | $$V_{AudioJack}=-2 \cdot V_{Audio}$$ | ||
- | $$-992mV < V_{AudioJack} < 992mV \left( High\;Gain \right)$$ | ||
- | $$-248mV < V_{AudioJack} < 248mV \left( Low\;Gain \right)\label{44}\tag{44}$$ | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | ===== 3.6. AWG Spectral Characteristics ===== | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | The Network Analyzer virtual instrument in WaveForms is used to perform synchronized signal synthesis and acquisition. It takes control of channel 1 of AWG and of both scope channels. Start/Stop frequencies are set to 100 Hz/25 MHz, respectively. Sinus amplitude is set to 1V. The characteristic is built in 100 steps. The 3dB bandwidth is 12 MHz with the coax cable and 9 MHz with the wire kit. The 0.5dB bandwidth is 4 MHz with the coax cable and 2.9 MHz with the wire kit. The 0.1dB is 1 MHz with the coax cable and 800 kHz with the wire kit. | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | ====== 4. Calibration Memory ====== | ||
- | |||
- | The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, | ||
- | |||
- | * 0.1% resistors and 1% capacitors in all the critical analog signal paths | ||
- | * Capacitive trimmers for balancing the Scope Input Divider and Gain Selection | ||
- | * No other mechanical trimmers (as these are big, expensive, unreliable and affected by vibrations, aging, and temperature drifts) | ||
- | * Software calibration, | ||
- | * User software calibration, | ||
- | |||
- | A software calibration is performed on each device as a part of the manufacturing test. AWG signals are passed to a reference instrument and reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Analog Discovery 2 device, as Factory Calibration. The WaveForms software allows the user performing an in-house calibration and overwrite the Calibration Data. Returning to Factory Calibration is always possible. | ||
- | |||
- | |||
- | The WaveForms Software reads the calibration parameters from the connected Analog Discovery 2 and uses them to correct both generated and acquired signals. | ||
- | |||
- | |||
- | ---- | ||
- | |||
- | ====== 5. Digital I/O ====== | ||
- | |||
- | [[analog_discovery_2: | ||
- | |||
- | General purpose FPGA I/O pins are used for Analog Discovery 2 Digital I/O. FPGA pins are set to SLOW slew rate and 4mA drive strength, with no internal pull. | ||
- | |||
- | PTC thermistors provide thermal protection in case of shortcuts. Schottky Diodes double the internal FPGA ESD protection diodes for increasing the acceptable current in case of overvoltage. Nominal resistance of the PTCs (220Ω) and parasitical capacitance of the Schottky diodes (2.2pF) and FPGA pins (10pF) limit the bandwidth of the input pins. For output pins, the PTCs and the load impedance limit the bandwidth and power. | ||
- | |||
- | Input and output pins are LVCMOS3V3. Inputs are 5V tolerant. Overvoltage up to ±20V is supported. | ||
- | |||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | |||
- | ====== 6. Power Supplies and Control ====== | ||
- | |||
- | This block includes all power monitoring and control circuitry, internal power supplies, and user power supplies. | ||
- | |||
- | |||
- | |||
- | ===== 6.1. USB Power Control ===== | ||
- | |||
- | As shown in [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The external power input is protected against reverse voltage; Q4 turns OFF if a floating power supply with negative polarity on central pin of J4 is used. However, the device is not protected for a very unlikely use case: | ||
- | |||
- | * Analog Discovery 2 connected to the USB port of a PC which has GND connected to EARTH | ||
- | * External power supply with negative polarity on central pin of J4 and with exterior pin connected to EARTH. | ||
- | |||
- | In this case, the external EARTH loop acts as a shortcut of Q4. | ||
- | |||
- | [[http:// | ||
- | * Window monitoring with minimum processor I/O | ||
- | * Individually monitoring N rails with only N + 1 processor I/O | ||
- | * 400 mV ± 0.275% threshold at VDD = 3.3 V, 25°C | ||
- | * Supply range: 1.7 V to 5.5 V | ||
- | * Low quiescent current: 8.55 μA maximum | ||
- | * Input range includes ground | ||
- | * Internal hysteresis: 9.2 mV typical | ||
- | * Low input bias current: ±2.5 nA maximum | ||
- | * Open-drain outputs | ||
- | * Power good indication output | ||
- | * Designated over voltage indication output | ||
- | * Low profile (1 mm), 6-lead TSOT package | ||
- | |||
- | IC48 drives PWRGD output HIGH (turning IC26 ON) when Vext is in the range: | ||
- | |||
- | $$4.11V=400mV \cdot \frac {R_{248} + R_{249}+R_{273}}{R_{249} + R_{273}} < V_{ext} < 400mV \cdot \frac {R_{248} + R_{249} + R_{273}}{R_{273}}=5.76V\label{45}\tag{45}$$ | ||
- | |||
- | The Analog Discovery 2 exhibits two main powering modes: USB and External. Temporary modes (Racing OFF, USB OFF and Racing) are explained here for design clarifications, | ||
- | |||
- | * **Racing OFF** – immediately after reset, before FPGA is programmed, if an external power supply is attached and in the right range (PWRGD = HIGH). | ||
- | * **USB OFF** – immediately after reset, before FPGA is programmed, if external power supply is missing or out-of-range (PWRGD = LOW). | ||
- | * **USB** – all the power is drained from the Vbus (IC21 = ON, IC26 = OFF). The external power supply is either missing or out of the right voltage range. The power available for both User Supplies is limited to 0.7W. | ||
- | * **Racing** – when external power supply is in the right voltage range (PWRGD = HIGH), before WaveForms stops the USB Power Controller. During racing mode, both USB Power Controller (IC21) and External Power controller (IC26) are ON, the device drains power from whatever supply has a higher voltage (D28 and D29 work as a maxim voltage detector). The Racing mode is temporary, it ends when the FPGA is configured and communicates with the WaveForms software. During Racing mode, the power available for User Supplies is limited. | ||
- | * **External** – the device is powered from an external supply (via the 5V DC connector and IC26). Vext is in the range shown by equation \ref{45} (PWRGD = HIGH, and WaveForms already stopped the USB Power Controller (IC21). The User Supplies current and power limits are increased to 700mA or 2.1W each. The only circuit still supplied from the USB VBUS is the USB controller (IC41). | ||
- | |||
- | At Power ON, the FPGA is not programmed, EN_VBUS is HiZ, the pulldown resistor R246 turns Q1 OFF, IC21 is ON via R174. The Analog Discovery 2 starts in **USB OFF** mode (when PWRGD = LOW) or **Racing OFF** mode (when PWRGD = HIGH). The WaveForms software first configures the FPGA, and the device turns into **USB** or **Racing** mode, depending on presence/ | ||
- | |||
- | If external Power Supply is attached after WaveForms started and runs several instruments, | ||
- | |||
- | However, removing the external power supply during **External** mode is not seamless. Only the USB controller keeps working (as supplied from the USB port). The FPGA gets unpowered and loses configuration data. The device stops all the instruments, | ||
- | |||
- | An [[http:// | ||
- | |||
- | Remarkable ADM1177 features are: | ||
- | * Safe live board insertion and removal | ||
- | * Supply voltages from 3.15 V to 16.5 V | ||
- | * Precision current sense amplifier | ||
- | * 12-bit ADC for current and voltage read | ||
- | * Adjustable analog current limit with circuit breaker | ||
- | * ±3% accurate hot swap current limit level | ||
- | * Fast response limits peak fault current | ||
- | * Automatic retry or latch-off on current fault | ||
- | * Programmable hot swap timing via TIMER pin | ||
- | * Soft start pin for reference adjustment and programming of initial current ramp rate | ||
- | * I2C fast mode-compliant interface (400 kHz maximum) | ||
- | |||
- | When enabled, (in **USB** or **Racing** modes), IC21 limits the current consumed from the USB port to: | ||
- | |||
- | $${I_{limit}} = \frac{{100mV}}{{{R_{173}}}} = \frac{{100mV}}{{0.1\Omega }} = 1A\label{46}\tag{46}$$ | ||
- | |||
- | |||
- | For a maximum time of: | ||
- | |||
- | $$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{80}=21.7 \left[ ms / \mu F \right] \cdot 0.47\mu F =10.2ms\label{47}\tag{47}$$ | ||
- | |||
- | If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, | ||
- | |||
- | $$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ \frac{ms}{\mu F} \right] \cdot 0.47 \mu F = 258.5ms\label{48}\tag{48}$$ | ||
- | |||
- | To avoid high inrush currents at hot swap, Soft Start circuitry limits the current slope to: | ||
- | |||
- | $$\frac {dI_{limit}}{dt} = \frac {10 \mu A}{C_{81}} \cdot \frac {1}{10 \cdot R_{173}} =212 \frac {mA}{ms} \label{49}\tag{49}$$ | ||
- | |||
- | If the current drops below $\; | ||
- | |||
- | Similarly, IC26 (in **Racing** or **External** modes), limits the current consumed from the external power supply to: | ||
- | |||
- | $${I_{limit}} = \frac {100mV}{R_{247}} = \frac {100mV}{0.036 \Omega} = 2.78A\label{50}\tag{50}$$ | ||
- | |||
- | ${t_{fault}}$ and ${t_{cool}}$ are same as for IC21, and the current slope limit is: | ||
- | |||
- | $$\frac {dI_{limit}}{dt} = \frac{10\mu A}{C_{432}} \cdot \frac{1}{10 \cdot R_{247}}=591 \frac{mA}{ms}\label{51}\tag{51}$$ | ||
- | |||
- | The Analog Discovery 2 user pins are overvoltage protected. Overvoltage (or ESD) diodes short when a user pin is overdriven by the external circuitry (Circuit Under Test), back powering the input/ | ||
- | |||
- | ---- | ||
- | ===== 6.2. Analog Supplies Control ===== | ||
- | |||
- | During **USB** mode, the FPGA constantly reads from IC21 the current value through R173. (Optionally displayed on Main Window/ | ||
- | |||
- | [[http:// | ||
- | * Low RDSon of 12mΩ | ||
- | * Low input voltage range: 1.8V to 5.5V | ||
- | * 1.2V logic compatible enable logic | ||
- | * Overtemperature protection | ||
- | * Ultra-small 1.0mmX1.5mm, | ||
- | |||
- | {{ : | ||
- | // | ||
- | ---- | ||
- | ===== 6.3. User Supplies Control ===== | ||
- | |||
- | IC27 in [[analog_discovery_2: | ||
- | |||
- | * Controls supply voltages from 4 V to 60 V | ||
- | * Gate drive for low voltage drop reverse supply protection | ||
- | * Gate drive for P-channel FETs | ||
- | * Inrush current limiting control | ||
- | * Adjustable current limit | ||
- | * Foldback current limiting | ||
- | * Automatic retry or latch-off on current fault | ||
- | * Programmable current-limit timer for safe operating area (SOA) | ||
- | * Power-good and fault outputs | ||
- | * Analog undervoltage (UV) and overvoltage (OV) protection | ||
- | * 16-lead 3x3mm LFCSP package | ||
- | * 16-lead QSOP package | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | IC27 limits the current consumed by both user power supplies together. The WaveForms software commands the FPGA to change the limit, depending on the power mode. | ||
- | |||
- | During **USB** and **Racing** modes, SET_ILIM_USR pin is driven LOW by the FPGA. The voltage at the ISET pin of IC27 is: | ||
- | |||
- | $${V_{Iset}} = \frac{{\frac{{{V_{cap}}}}{{{R_{253}}}}}}{{\frac{1}{{{R_{253}}}} + \frac{1}{{{R_{254}}}} + \frac{1}{{{R_{255}}}}}} = \frac{{\frac{{3.6V}}{{10k\Omega }}}}{{\frac{1}{{10k\Omega }} + \frac{1}{{1.74k\Omega }} + \frac{1}{{22.6k\Omega }}}} = 0.5V\label{52}\tag{52}$$ | ||
- | |||
- | The current limit is set to: | ||
- | |||
- | $$I_{limit}= \frac{V_{Iset}}{40 \cdot R_{21}} = \frac{0.5V}{40 \cdot 0.043 \Omega} = 290mA\label{53}\tag{53}$$ | ||
- | |||
- | During **External** and **OFF** modes, SET_ILIM_USR pin is driven HiZ by the FPGA. The voltage at the ISET pin of IC27 is: | ||
- | |||
- | $$V_{Iset}= \frac {V_{cap} \cdot R_{255}}{R_{253} + R_{255}} = \frac{3.6V \cdot 22.6k \Omega }{10k \Omega + 22.6k \Omega} = 2.5V\label{54}\tag{54}$$ | ||
- | |||
- | The current limit is set to: | ||
- | |||
- | $$I_{limit}= \frac {V_{Iset}}{40 \cdot R_{21}} = \frac {2.5V}{40 \cdot 0.043 \Omega} = 1.45A\label{55}\tag{55}$$ | ||
- | |||
- | In both cases, ${I_{limit}}$ **is allowed** for a maximum time of: | ||
- | |||
- | $$t_{fault}=21.7 \left[ ms / \mu F \right] \cdot C_{170} = 21.7 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 102ms\label{56}\tag{56}$$ | ||
- | |||
- | If the consumed current does not fall below ${I_{limit}}$ before ${t_{fault}}$, | ||
- | |||
- | $$t_{cool}=550 \left[ ms / \mu F \right] \cdot C_{80} = 550 \left[ ms / \mu F \right] \cdot 4.7 \mu F = 2.585s\label{57}\tag{57}$$ | ||
- | |||
- | |||
- | Soft Start is not used; C183 is a No Load. | ||
- | |||
- | If the current drops below ${I_{limit}}$ before ${t_{fault}}$, | ||
- | |||
- | The current limited by equations \ref{53} and \ref{55} is shared by both positive and negative user power supplies. After considering the efficiency of the user supply stages, about 100mA is available for user in both supplies together, in **USB Only** mode. In **External** mode, the current/ | ||
- | |||
- | ---- | ||
- | ===== 6.4. User Voltage Supplies ===== | ||
- | |||
- | The user power supplies [[analog_discovery_2: | ||
- | |||
- | * 1.4A current limit | ||
- | * Minimum input voltage 1.8V | ||
- | * Pin-selectable 650 kHz or 1.3 MHz PWM frequency | ||
- | * Adjustable output voltage up to 20 V | ||
- | * Adjustable soft start | ||
- | * Undervoltage lockout | ||
- | |||
- | IC46A/B op amps insert the command voltages $V_{SET+\_USR}$ and $V_{SET-\_USR}$, | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | Since the op amps are included in negative feedback loops, the input pins voltages are equal: | ||
- | |||
- | $${V_{ + IC46A}} = \frac{{\frac{{{V_{OUT + \_USR}}}}{{{R_{188}}}} + \frac{{{V_{SET + \_USR}}}}{{{R_{193}}}}}}{{\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}}}} = {V_{ - IC46A}} = \frac{{\frac{{{V_{FB}}}}{{{R_{266}}}}}}{{\frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}}}\label{58}\tag{58}$$ | ||
- | |||
- | $${V_{ + IC46B}} = \frac{{\frac{{{V_{OUT - \_USR}}}}{{{R_{187}}}} + \frac{{{V_{FB}}}}{{{R_{270}}}}}}{{\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}}}} = {V_{ - IC46B}} = \frac{{\frac{{{V_{SET - \_USR}}}}{{{R_{190}}}}}}{{\frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}}}\label{59}\tag{59}$$ | ||
- | |||
- | The input impedances for the op amps are matched: | ||
- | |||
- | $$\frac{1}{{{R_{188}}}} + \frac{1}{{{R_{193}}}} = \frac{1}{{{R_{265}}}} + \frac{1}{{{R_{266}}}}\label{60}\tag{60}$$ | ||
- | |||
- | $$\frac{1}{{{R_{187}}}} + \frac{1}{{{R_{270}}}} = \frac{1}{{{R_{72}}}} + \frac{1}{{{R_{190}}}}\label{61}\tag{61}$$ | ||
- | |||
- | The user voltages are: | ||
- | |||
- | $$V_{OUT\; | ||
- | |||
- | $$V_{OUT\; | ||
- | |||
- | Where: | ||
- | |||
- | $${V_{FB}} = 1.235V\; | ||
- | |||
- | IC43 [[analog_discovery_2: | ||
- | |||
- | $$0 < V_{SET + \_USR},\; V_{SET - \_USR} < 1.2V\label{65}\tag{65}$$ | ||
- | |||
- | Which would allow output voltages to be set in the ranges: | ||
- | |||
- | $$ - 0.51V \le {V_{SET + \_USR}} < 5.33V\label{66}\tag{66}$$ | ||
- | |||
- | $$0.51V \ge \; V_{SET - \_USR} > - 5.33V\label{67}\tag{67}$$ | ||
- | |||
- | The margins allow for compensating the components’ tolerances. After calibration, | ||
- | |||
- | Each supply can be disabled by the FPGA. | ||
- | |||
- | |||
- | |||
- | ---- | ||
- | |||
- | ===== 6.5. Internal Power Supplies===== | ||
- | |||
- | ==== 6.5.1. Analog Supplies ==== | ||
- | |||
- | Analog supplies need to have very low ripple to prevent noise from coupling into analog signals. Ferrite beads are used to filter the remaining switching noise and to separate the power supplies that go to the main analog circuit blocks, to avoid crosstalk. | ||
- | |||
- | The 3.3V [[analog_discovery_2: | ||
- | |||
- | * Input voltage: 2.3 V to 5.5 V | ||
- | * Peak efficiency: 95% | ||
- | * 3 MHz fixed frequency operation | ||
- | * Typical quiescent current: 24 μA | ||
- | * Very small solution size | ||
- | * 6-lead, 1 mm × 1.5 mm WLCSP package | ||
- | * Fast load and line transient response | ||
- | * 100% duty cycle low dropout mode | ||
- | * Internal synchronous rectifier, compensation, | ||
- | * Current overload and thermal shutdown protections | ||
- | * Ultra-low shutdown current: 0.2 μA (typical) | ||
- | * Forced PWM and automatic PWM/PSM modes | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The -3.3V analog power supply [[analog_discovery_2: | ||
- | |||
- | * 1.2 A maximum load current | ||
- | * ±2% output accuracy over temperature range | ||
- | * 1.4 MHz switching frequency | ||
- | * High efficiency up to 91% | ||
- | * Current-mode control architecture | ||
- | * Output voltage from 0.8 V to 0.85 × VIN | ||
- | * Automatic PFM/PWM mode switching | ||
- | * Integrated high-side MOSFET | ||
- | * Internal compensation and soft start | ||
- | * Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD) | ||
- | * Available in ultrasmall, 6-lead TSOT package | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The Output voltage is set with an external resistor divider from Vout to FB: | ||
- | |||
- | $$\frac{{{R_{180}}}}{{{R_{181}}}} = \;\frac{{ - {V_{out}} - {V_{ref}}}}{{{V_{ref}}}}\label{68}\tag{68}$$ | ||
- | |||
- | Choosing $R_{181} = 10.2k{\text{\Omega }}$: | ||
- | |||
- | $$R_{180}= \frac{3.3V-0.8V}{0.8V} \cdot 10.2k \Omega = 31.87k \Omega \label{69}\tag{69}$$ | ||
- | |||
- | Closest standard value is $R_{180} = 31.6k{\text{\Omega }}$ | ||
- | |||
- | The 5.5V and -5.5V supplies [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The output current in a Sepic is discontinuous which results in a higher output ripple. To lower this ripple an additional output filter is added to the positive rail. | ||
- | |||
- | For more information see application note: [[http:// | ||
- | |||
- | Setting the Output Voltage: | ||
- | |||
- | $$\frac{{{R_{184}}}}{{{R_{185}}}} = \; | ||
- | |||
- | Choosing ${R_{185}} = 13.7k\Omega$: | ||
- | |||
- | $$R_{184}= \frac{5.5V-1.235V}{1.235V} \cdot 13.7k \Omega = 47.31k \Omega\label{71}\tag{71}$$ | ||
- | |||
- | Closest standard value is ${R_{184}} = 47.5k\Omega$ | ||
- | |||
- | |||
- | ==== 6.5.2. Digital Supplies ==== | ||
- | |||
- | The 1V digital supply [[analog_discovery_2: | ||
- | |||
- | * 1.25A continuous output current | ||
- | * 145 mΩ and 70 mΩ integrated MOSFETs | ||
- | * Input voltage range from 2.3 V to 5.5 V; output voltage from 0.6 V to VIN | ||
- | * 1.2 MHz fixed switching frequency; Selectable PWM or PFM mode operation | ||
- | * Current mode architecture | ||
- | * Integrated soft start; Internal compensation | ||
- | * UVLO, OVP, OCP, and thermal shutdown | ||
- | * 10-lead, 3 mm × 3 mm LFCSP_WD package | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | The 3.3V digital supply [[analog_discovery_2: | ||
- | |||
- | * Seamless transition between modes | ||
- | * 38 μA typical quiescent current | ||
- | * 2.5 MHz operation enables 1.5 μH inductor | ||
- | * Input voltage: 2.3 V to 5.5 V; | ||
- | * Fixed output voltage: 3.3 V | ||
- | * Forced fixed frequency | ||
- | * Internal compensation | ||
- | * Soft start | ||
- | * Enable/ | ||
- | * Overtemperature protection | ||
- | * Short-circuit protection | ||
- | * Reverse current capability | ||
- | * Undervoltage lockout protection | ||
- | * Small 10-lead 3 mm × 3 mm package, 1 mm height profile | ||
- | * Compact PCB footprint | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | |||
- | The main requirement for the 3.3V digital supply is the reverse current capability. When a user pin is overdriven the protection diode opens and back powers circuitry connected to this supply. If the back powered energy is higher than the used energy the regulator delivers it to its input, preventing the 3.3V from rising. | ||
- | |||
- | The 1.8V digital power supply [[analog_discovery_2: | ||
- | |||
- | The ADP2138 also features: | ||
- | |||
- | * Input voltage: 2.3 V to 5.5 V | ||
- | * Peak efficiency: 95% | ||
- | * Typical quiescent current: 24 μA | ||
- | * Fast load and line transient response | ||
- | * 100% duty cycle low dropout mode | ||
- | * Internal synchronous rectifier, compensation, | ||
- | * Current overload and thermal shutdown protections | ||
- | * Ultra-low shutdown current: 0.2 μA (typical) | ||
- | * Forced PWM and automatic PWM/PSM modes | ||
- | |||
- | {{ : | ||
- | // | ||
- | |||
- | ---- | ||
- | ===== 6.6. Temperature Measurement ===== | ||
- | |||
- | The Analog Discovery 2 uses the [[http:// | ||
- | |||
- | * 10-bit temperature-to-digital converter | ||
- | * Temperature range: −40°C to +125°C | ||
- | * Typical accuracy of ±0.5°C at +40°C | ||
- | * SMBus/ | ||
- | * Temperature conversion time: 29μs (typical) | ||
- | * Space-saving 5-lead SOT-23 package | ||
- | * Pin-selectable addressing via AS pin | ||
- | |||
- | {{ : | ||
- | // | ||
- | ---- | ||
- | ====== 7. USB Controller ====== | ||
- | |||
- | The USB interface performs two tasks: | ||
- | * **Programming the FPGA:** There is no non-volatile FPGA configuration memory on the Analog Discovery. The WaveForms software identifies the connected device and downloads an appropriate .bit file at power-up, via a Digilent USB-JTAG interface. Adept run-time is used for low level protocols. | ||
- | * **Data exchange:** All instrument configuration data, acquired data and status information is handled via a Digilent synchronous parallel bus and USB interface. Speed up to 20MB/sec. is reached, depending on USB port type and load as well as PC performance. | ||
- | |||
- | |||
- | ---- | ||
- | |||
- | |||
- | ====== 8. FPGA ====== | ||
- | |||
- | The core of the Analog Discovery 2 is the Xilinx [[http:// | ||
- | |||
- | * Clock management (12 MHz and 60 MHz for USB communication, | ||
- | * Acquisition control and Data Storage (Scope and Logic Analyzer) | ||
- | * Analog Signal synthesis (look-up tables, AM/FM modulation for AWG) | ||
- | * Digital signal synthesis (for pattern generator) | ||
- | * Trigger system (trigger detection and distribution for all instruments ) | ||
- | * Power supplies control and instruments enabling | ||
- | * Power and temperature monitoring | ||
- | * Calibration memory control | ||
- | * Communication with the PC (settings, status data) | ||
- | |||
- | Block and Distributed RAM of the FPGA are used for signal synthesis and acquisition. Multiple configuration files are available through the WaveForms software to allocate the RAM resources according to the application. | ||
- | |||
- | Detail of the trigger system is shown in [[analog_discovery_2: | ||
- | |||
- | {{ : | ||
- | // | ||
- | ---- | ||
- | ====== 9. Features and Performances ====== | ||
- | |||
- | This chapter shows the features and performances as described in the Analog Discovery 2 Datasheet. Footnotes add detailed information and annotate the HW description in this Manual. | ||
- | |||
- | |||
- | ===== 9.1. Analog Inputs (Scope) ===== | ||
- | |||
- | * Channels: 2 | ||
- | * Channel type: differential((See note in section 2. Scope)) | ||
- | * Resolution: | ||
- | * Absolute Resolution(scale ≤0.5V/ | ||
- | * Absolute Resolution(scale≥1V/ | ||
- | * Accuracy (scale≤0.5V/ | ||
- | * Accuracy (scale≥1V/ | ||
- | * CMMR (typical): ±0.5% | ||
- | * Sample rate (real time): 100MS/s | ||
- | * Input impedance: 1MΩ||24pF | ||
- | * Scope scales: 500uV to 5V/ | ||
- | * Analog bandwidth with Discovery BNC adapter((The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see [[analog_discovery_2: | ||
- | * Analog bandwidth with Wire Kit((The Scope bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances (see [[analog_discovery_2: | ||
- | * Input range: ±25V (±50V diff((As shown in Fig. 12, a ±50V differential input signal does not fit in a single scope screen (ADC range). However, Vertical Position setting allows visualization of either +50V or -50V levels.))) | ||
- | * Input protected to: ±50V; | ||
- | * Buffer size/ | ||
- | * Triggering: edge, pulse, transition, hysteresis, etc.((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Cross-triggering with Logic Analyzer, Waveform Generator, Pattern Generator or external trigg((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Sampling modes: average, decimate, min/ | ||
- | * Mixed signal visualization (analog and digital signals share same view pane)((In mixed signal mode, the scope and Digital I/O acquisition blocks use the same reference clock, for synchronization.)) | ||
- | * Real-time views: FFTs, XY plots, Histograms and other((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)) | ||
- | * Multiple math channels with complex functions. | ||
- | * Cursors with advanced data measurements((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)) | ||
- | * Captured data files can be exported in standard formats((This functionality is implemented by WaveForms software, in the PC.)) | ||
- | * Scope configurations can be saved, exported and imported((This functionality is implemented by WaveForms software, in the PC.)) | ||
- | |||
- | |||
- | |||
- | |||
- | |||
- | ---- | ||
- | ===== 9.2. Analog Outputs (Arbitrary Waveform Generator) ===== | ||
- | |||
- | * Channels: 2 | ||
- | * Channel type: single ended | ||
- | * Resolution: | ||
- | * Absolute Resolution(amplitude ≤1V): | ||
- | * Absolute Resolution(amplitude > | ||
- | * Accuracy - typical (|Vout| ≤ 1V): ±10mV ± 0.5% | ||
- | * Accuracy - typical (|Vout| > 1V): ±25mV ± 0.5% | ||
- | * Sample rate (real time): 100MS/ | ||
- | * AC amplitude (max): ±5 V((The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.)) | ||
- | * DC Offset (max): ±5 V((The AWG output voltage is limited to ±5V. This refers to the sum of AC signal and DC offset.)) | ||
- | * Analog bandwidth with Discovery BNC adapter((The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see [[analog_discovery_2: | ||
- | * Analog bandwidth with Wire Kit((The AWG bandwidth depends on probes. The Analog Discovery wire kit is an affordable, easy-to-use solution, but it limits the frequency, noise, and crosstalk performances. With coax probes and Analog Discovery BNC adapter, the 0.5dB AWG bandwidth is 4MHz (see [[analog_discovery_2: | ||
- | * Slew rate (10V step): 400V/μs | ||
- | * Buffer size/ | ||
- | * Standard waveforms: sine, triangle, sawtooth, etc. | ||
- | * Advanced waveforms: Sweeps, AM, FM((Real time implemented in the FPGA configuration.)). | ||
- | * User-defined arbitrary waveforms: defined within WaveForms software user interface or using standard tools (e.g. Excel)((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | | ||
- | |||
- | ---- | ||
- | ===== 9.3. Logic Analyzer ===== | ||
- | |||
- | * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)) | ||
- | * Sample rate (real time): 100MS/s | ||
- | * Buffer size/ | ||
- | * Input logic: LVCMOS (1.8V/3.3V, 5V tolerant) | ||
- | * Multiple trigger options including pin change, bus pattern, etc((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Cross-triggering between Analog input channels, Logic Analyzer, Pattern Generator or external trigger((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Interpreter for SPI, I2C, UART, Parallel bus((This functionality is implemented by WaveForms software in the PC, using the buffered data from the FPGA. After a acquiring a complete data buffer at the FPGA level and uploading it to the PC, the data is processed and displayed, while a new acquisition is started.)). | ||
- | * Data file import/ | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.4. Digital Pattern Generator ===== | ||
- | |||
- | * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)) | ||
- | * Sample rate (real time): 100MS/s | ||
- | * Algorithmic pattern generator (no buffers used)((Real time implemented in the FPGA configuration.)) | ||
- | * Custom pattern buffer/ch.: up to 16Ksamples((Default Pattern Generator buffer size is 1kSamples/ | ||
- | * Output logic standard: LVCMOS (3.3V, 12mA) | ||
- | * Data file import/ | ||
- | * Customized visualization for signals and busses((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | |||
- | ---- | ||
- | ===== 9.5. Digital I/O ===== | ||
- | |||
- | * Channels: 16 (shared)((All digital I/O pins are always available as inputs, to be acquired and displayed in the Logic Analyzer and Static I/O. The user selects which pins are also used as outputs, by the Pattern Generator or Static I/O. When a signal is driven by both Pattern Generator and Static I/O, the Static I/O has priority, except if Static I/O attempts to drive a HiZ value.)). | ||
- | * Input logic: LVCMOS (1.8V/3.3V, 5V tolerant) | ||
- | * Output logic standard: LVCMOS (3.3V, 12mA) | ||
- | * Virtual I/O devices (buttons, switches & displays)((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Customized visualization options available((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.6. Power Supplies ===== | ||
- | |||
- | * Voltage range: 0.5V…5V and -0.5V…-5V((WaveForms allows setting the user voltages in the range 0V…5V respectively -0V…-5V. However, voltages below 0.5V, respectively above -0.5V might have excessive ripple and should be used with caution.)). | ||
- | * Pmax (USB powered): | ||
- | * Imax (USB powered): | ||
- | * Pmax (AUX powered): | ||
- | * Imax (AUX powered): | ||
- | * Accuracy (no load): | ||
- | * Output impedance: 50mΩ (typical) | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.7. Network Analyzer*³ ===== | ||
- | |||
- | * Shared instruments: | ||
- | * Frequency sweep range: 1Hz to 10MHz | ||
- | * Frequency steps: 5 … 1000((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Settable input amplitude and offset | ||
- | * Analog input records response at each frequency((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Available diagrams: | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.8. Voltmeters° ===== | ||
- | |||
- | * Channels (shared with scope): 2 | ||
- | * Channel type: differential | ||
- | * Measurements: | ||
- | * Resolution: | ||
- | * Accuracy (scale ≤0.5V/ | ||
- | * Accuracy (scale ≥1V/div): ±50mV | ||
- | * Input impedance: 1MΩ || 24pF | ||
- | * Input range: ±25V (±50V diff) | ||
- | * Input protected to: ±50V | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.9. Spectrum Analyzer°°===== | ||
- | |||
- | * Channels (shared with scope): 2 | ||
- | * Power spectrum algorithms: FFT, CZT((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Frequency range modes: center/ | ||
- | * Frequency scales: linear, logarithmic((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Vertical axis options: voltage-peak, | ||
- | * Windowing: options: rectangular, | ||
- | * Cursors and automatic measurements: | ||
- | * Data file import/ | ||
- | |||
- | |||
- | ---- | ||
- | ===== 9.10. Other features ===== | ||
- | |||
- | * USB power option; all needed cables included. | ||
- | * External supply option: | ||
- | * High-speed USB2 interface for fast data transfer | ||
- | * Waveform Generator output played on stereo audio jack | ||
- | * Trigger in/trigger out allows multiple instruments to be linked((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Cross triggering between instruments((Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-triggering of different instruments within the Analog Discovery device. Using external Trigger inputs/ | ||
- | * Help screens, including contextual help((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | * Instruments and workspaces can be individually configured; configurations can be exported((This functionality is implemented by WaveForms software, in the PC.)). | ||
- | |||
- | |||
- | |||
- | ---- | ||
- | |||
- | *³The Network Analyzer instrument in WaveForms uses a channel of Analog Outputs (AWG) and all Analog Inputs (Scope) hardware resources. When it starts running, all other instruments using the same HW resources (competing instruments: | ||
- | |||
- | °This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state. | ||
- | |||
- | °°This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state. | ||
- | |||
- | **Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania** |