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programmers:jtag-smt2:reference-manual [2023/06/15 16:41] – [Mounting to Host PCBs] James Colvinprogrammers:jtag-smt2:reference-manual [2024/02/22 01:07] (current) – some reformatting James Colvin
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 ====== JTAG SMT2 Reference Manual ====== ====== JTAG SMT2 Reference Manual ======
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 +The Joint Test Action Group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx tools, including iMPACT, Chipscope, eFuse, Vivado and EDK. Users can load the module directly onto a target board and reflow it like any other component. 
  
 {{Digilent Image Gallery  {{Digilent Image Gallery 
 | image = {{jtag_smt2/smt2-obl-600.png?direct|}} | image = {{jtag_smt2/smt2-obl-600.png?direct|}}
 +| image = {{ :programming_solutions:jtag_smt2:ove1.png?300|}}
 }} }}
  
-{{ :programming_solutions:jtag_smt2:ove1.png?300|}} 
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-=== Download this Reference Manual === 
-  * {{ :reference:programmers:jtag-smt2:jtag-smt2_rm.pdf | PDF}} 
  
-The Joint Test Action Group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx tools, including iMPACT, Chipscope, eFuse, Vivado and EDK.  Users can load the module directly onto a target board and reflow it like any other component. 
  
 +==== Overview ====
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 The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming.  The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming. 
 The SMT2 module is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc. The SMT2 module is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc.
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   * Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs   * Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs
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   * A similar circuit is available as a stand-alone programming cable; see Digilent’s JTAG-HS2.   * A similar circuit is available as a stand-alone programming cable; see Digilent’s JTAG-HS2.
  
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 Users can connect JTAG signals directly to the corresponding FPGA signals as shown in Figure 1. For best results, mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2 clear.  Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed. Users can connect JTAG signals directly to the corresponding FPGA signals as shown in Figure 1. For best results, mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2 clear.  Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed.
 The SMT2 improves upon the SMT1 with the addition of three general purpose IO pins (GPIO0 – GPIO2) and support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes. The SMT2 improves upon the SMT1 with the addition of three general purpose IO pins (GPIO0 – GPIO2) and support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.
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 In addition to supporting JTAG, the JTAG-SMT2 also features eight highly configurable Serial Peripheral Interface (SPI) ports that allow communication with virtually any SPI peripheral. (See figure 2) All eight SPI ports share the same SCK, MOSI, and MISO pins, so users may enable only one port at any given time.  The table in figure 3 summarizes the features supported by each port. The HS2 supports SPI modes 0, 1, 2, and 3. In addition to supporting JTAG, the JTAG-SMT2 also features eight highly configurable Serial Peripheral Interface (SPI) ports that allow communication with virtually any SPI peripheral. (See figure 2) All eight SPI ports share the same SCK, MOSI, and MISO pins, so users may enable only one port at any given time.  The table in figure 3 summarizes the features supported by each port. The HS2 supports SPI modes 0, 1, 2, and 3.
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 |  __Figure 3__                                                                                                                                                                                                    ||||||||| |  __Figure 3__                                                                                                                                                                                                    |||||||||