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programmers:jtag-hs2:reference-manual [2021/05/14 23:04] – ↷ Page moved from reference:programmers:jtag-hs2:reference-manual to programmers:jtag-hs2:reference-manual Arthur Brownprogrammers:jtag-hs2:reference-manual [2023/11/09 23:35] (current) – [JTAG-HS2 Reference Manual] Arthur Brown
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-=== Download the Reference Manual === 
-  * {{ :reference:programmers:jtag-hs2:jtag-hs2_rm.pdf | PDF}} 
 ==== Features ==== ==== Features ====
  
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-====== Software Support ======+===== Software Support =====
  
 In addition to working seamlessly with all Xilinx tools, Digilent’s Adept software and the Adept software development kit (SDK) support the HS2 cable.  For added convenience customers may freely downloaded the SDK from Digilent’s website. This Adept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain.  In addition to working seamlessly with all Xilinx tools, Digilent’s Adept software and the Adept software development kit (SDK) support the HS2 cable.  For added convenience customers may freely downloaded the SDK from Digilent’s website. This Adept software includes a full-featured programming environment and a set of public application programming interfaces (API) that allow user applications to directly drive the JTAG chain. 
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-======  IEEE 1149.7-2009 Compatibility ======+=====  IEEE 1149.7-2009 Compatibility =====
  
 The JTAG-HS2 supports several scan formats including; the JScan0-JScan3, MScan, and OScan0 - OScan7.  It is capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 – T4 JTAG Target Systems (TS). (See Figure 5 & 6) The JTAG-HS2 supports several scan formats including; the JScan0-JScan3, MScan, and OScan0 - OScan7.  It is capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0 – T4 JTAG Target Systems (TS). (See Figure 5 & 6)
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-====== Design Notes ======+===== Design Notes =====
  
 The JTAG-HS2 uses high speed three-state buffers to drive the TMS, TDI, and TCK signals. These buffers are capable of sourcing or sinking a maximum of 50 mA of current. The HS2 has 100 ohm resistors between the output of the buffers and the I/O pins to ensure the cable does not exceed the maximum limit. To further limit short circuit current additional resistance may be placed in series with the I/O pins of the HS2 and the target board. However, Digilent recommends limiting the amount of additional resistance to 100 ohms or less as higher resistance may result in degraded operation. The JTAG-HS2 uses high speed three-state buffers to drive the TMS, TDI, and TCK signals. These buffers are capable of sourcing or sinking a maximum of 50 mA of current. The HS2 has 100 ohm resistors between the output of the buffers and the I/O pins to ensure the cable does not exceed the maximum limit. To further limit short circuit current additional resistance may be placed in series with the I/O pins of the HS2 and the target board. However, Digilent recommends limiting the amount of additional resistance to 100 ohms or less as higher resistance may result in degraded operation.
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 The IEEE 1149.7-2009 specification requires any device that functions as a Debug and Test System (DTS) to provide a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-HS2 features weak pull-ups (100K ohm) on the TMS, TDI, TDO, and TCK signals. While not strictly required, the pull-ups on the TDI and TCK signals ensure that neither signal floats while another source is not actively driving them. The IEEE 1149.7-2009 specification requires any device that functions as a Debug and Test System (DTS) to provide a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-HS2 features weak pull-ups (100K ohm) on the TMS, TDI, TDO, and TCK signals. While not strictly required, the pull-ups on the TDI and TCK signals ensure that neither signal floats while another source is not actively driving them.
 +
 +{{ :programmers:jtag-hs2:jtag-input-output-stage.png?800 |}}
 +<html><center></html>//JTAG Input/Output Stage//<html></center></html>
  
 The JTAG-HS2 can interface scan chains that consist of one or more IEEE 1149-7 compatible Target Systems (TS). The devices in these chains communicate using the TMS, TDI, TDO, and TCK signals or they may communicate using only the TMS and TCK signals. Communication using only the TMS and TCK signals requires both the HS2 and TS to drive the TMS pin. The current scan format, bit period, and the level of the TCK pin determine which device is allowed to drive the TMS pin.  The JTAG-HS2 can interface scan chains that consist of one or more IEEE 1149-7 compatible Target Systems (TS). The devices in these chains communicate using the TMS, TDI, TDO, and TCK signals or they may communicate using only the TMS and TCK signals. Communication using only the TMS and TCK signals requires both the HS2 and TS to drive the TMS pin. The current scan format, bit period, and the level of the TCK pin determine which device is allowed to drive the TMS pin. 
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-====== Absolute Maximum Ratings ======+===== Absolute Maximum Ratings =====
  
 | **Symbol**                             | **Parameter**                                                  | **Condition**  | **Min**  | **Max**  | **Unit**  | | **Symbol**                             | **Parameter**                                                  | **Condition**  | **Min**  | **Max**  | **Unit**  |
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-====== DC Operating Characteristics ======+===== DC Operating Characteristics =====
  
 |  **Symbol**    |  **Parameter**                |  **Min**    |  **Typ**    |  **Max**    |  **Unit**  | |  **Symbol**    |  **Parameter**                |  **Min**    |  **Typ**    |  **Max**    |  **Unit**  |
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-====== AC Operating Characteristics ======+===== AC Operating Characteristics =====
  
 {{ :programming_solutions:jtag_hs2:ac1.png?300|}} {{ :programming_solutions:jtag_hs2:ac1.png?300|}}
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-====== Supported Target Devices ======+===== Programming Solutions Comparison Chart ===== 
 + 
 +{{ :programming_solutions:jtag_hs3:sol1.png?650&nolink |}} 
 + 
 +---- 
 + 
 +===== Supported Target Devices =====
  
 The JTAG-HS2 is capable of targeting the following Xilinx devices: The JTAG-HS2 is capable of targeting the following Xilinx devices: