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programmable-logic:usb104a7:reference-manual [2021/05/14 23:07] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:usb104a7:reference-manual [2022/09/12 12:29] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey
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 If the hub configuration/recovery select switch (SW1/4) is placed in the "HCFG" position at power-up, the Platform MCU configures it to automatically detect which power input source is used and correctly report whether the board is self or bus powered to the USB host. If the hub configuration/recovery select switch (SW1/4) is placed in the "HCFG" position at power-up, the Platform MCU configures it to automatically detect which power input source is used and correctly report whether the board is self or bus powered to the USB host.
  
-**Note:** //Switches SW1/3 and SW1/4 are intended for restoration of and updates to the Platform MCU firmware and the USB Hub configuration. Please reach out to Digilent Support on the Programmable Logic section of the [[https://forum.digilentinc.com|Digilent Forum]] in the event that your board needs to be reflashed. For normal operation, SW1/3 and SW1/4 should be left in the "NORM" and "HCFG" positions, respectively.//+**Note:** //Switches SW1/3 and SW1/4 are intended for restoration of and updates to the Platform MCU firmware and the USB Hub configuration. Please reach out to Digilent Support on the Programmable Logic section of the [[https://forum.digilent.com|Digilent Forum]] in the event that your board needs to be reflashed. For normal operation, SW1/3 and SW1/4 should be left in the "NORM" and "HCFG" positions, respectively.//
  
 When the USB104 A7 is turned on, the PMCU enumerates the pods attached to the USB104 A7's SYZYGY ports and retrieves their DNA, in order to correctly configure the variable supplies. When the USB104 A7 is turned on, the PMCU enumerates the pods attached to the USB104 A7's SYZYGY ports and retrieves their DNA, in order to correctly configure the variable supplies.
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 === 6.1. DPTI Parallel Data Transfer Interface === === 6.1. DPTI Parallel Data Transfer Interface ===
  
-The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. THe USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:+The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:
  
 {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}} {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}}