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programmable-logic:usb104a7:reference-manual [2021/05/14 23:04] – ↷ Page moved from reference:programmable-logic:usb104a7:reference-manual to programmable-logic:usb104a7:reference-manual Arthur Brownprogrammable-logic:usb104a7:reference-manual [2022/09/12 12:29] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey
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 If the hub configuration/recovery select switch (SW1/4) is placed in the "HCFG" position at power-up, the Platform MCU configures it to automatically detect which power input source is used and correctly report whether the board is self or bus powered to the USB host. If the hub configuration/recovery select switch (SW1/4) is placed in the "HCFG" position at power-up, the Platform MCU configures it to automatically detect which power input source is used and correctly report whether the board is self or bus powered to the USB host.
  
-**Note:** //Switches SW1/3 and SW1/4 are intended for restoration of and updates to the Platform MCU firmware and the USB Hub configuration. Please reach out to Digilent Support on the Programmable Logic section of the [[https://forum.digilentinc.com|Digilent Forum]] in the event that your board needs to be reflashed. For normal operation, SW1/3 and SW1/4 should be left in the "NORM" and "HCFG" positions, respectively.//+**Note:** //Switches SW1/3 and SW1/4 are intended for restoration of and updates to the Platform MCU firmware and the USB Hub configuration. Please reach out to Digilent Support on the Programmable Logic section of the [[https://forum.digilent.com|Digilent Forum]] in the event that your board needs to be reflashed. For normal operation, SW1/3 and SW1/4 should be left in the "NORM" and "HCFG" positions, respectively.//
  
 When the USB104 A7 is turned on, the PMCU enumerates the pods attached to the USB104 A7's SYZYGY ports and retrieves their DNA, in order to correctly configure the variable supplies. When the USB104 A7 is turned on, the PMCU enumerates the pods attached to the USB104 A7's SYZYGY ports and retrieves their DNA, in order to correctly configure the variable supplies.
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 === 6.1. DPTI Parallel Data Transfer Interface === === 6.1. DPTI Parallel Data Transfer Interface ===
  
-The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. THe USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:+The DPTI interface is an 8-bit wide parallel FIFO-style data interface supporting both asynchronous and synchronous modes. In FTDI terminology, DPTI is equivalent to "FT245-style Asynchronous or Synchronous FIFO Interface". It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller (connected to the FPGA on pin P17). In asynchronous mode, data transfer occurs on transitions of the read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read and free space for data to be written. The FPGA controls data transfer through read, write, and output enable signals. Data transfer speeds of up to 40 MB/s are supported in synchronous mode. This interface is summarized in Figure 6.1.1, below:
  
 {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}} {{ :reference:programmable-logic:usb104a7:usb104a7-dpti.png?nolink&600 |}}
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 Microblaze support for DPTI is provided by the AXI DPTI IP core which can be found in the [[https://github.com/Digilent/vivado-library|vivado-library]] repository on Digilent's GitHub. Microblaze support for DPTI is provided by the AXI DPTI IP core which can be found in the [[https://github.com/Digilent/vivado-library|vivado-library]] repository on Digilent's GitHub.
  
-The Digilent Adept Runtime can be used with the the Digilent Adept API in order to simplify the host side communication through DPTI. The Adept Runtime can be downloaded through the [[reference:software:adept:start|Adept]] wiki page. The Zmod ADC and Zmod DAC example projects, which can be found on the [[start|USB104 A7 Resource Center]] include example PC-side applications intended for receiving and transmitting data through the DPTI interface.+The Digilent Adept Runtime can be used with the the Digilent Adept API in order to simplify the host side communication through DPTI. The Adept Runtime can be downloaded through the [[software:adept:start|Adept]] wiki page. The Zmod ADC and Zmod DAC example projects, which can be found on the [[start|USB104 A7 Resource Center]] include example PC-side applications intended for receiving and transmitting data through the DPTI interface.
  
 **Note:** //A DSPI interface is also connected, but no demos are provided as of time of writing. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. The pulldown resistor on the SPI enable line means that the default interface is DPTI. SPIEN should be held low or not be driven by the FPGA while using DPTI.// **Note:** //A DSPI interface is also connected, but no demos are provided as of time of writing. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. The pulldown resistor on the SPI enable line means that the default interface is DPTI. SPIEN should be held low or not be driven by the FPGA while using DPTI.//
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 A SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Bank 15 of the FPGA is dedicated to the Zmod port and is powered by a dedicated adjustable rail, configured by the Platform MCU as the USB104 A7 is powered on. Template constraints for the Zmod port can be found in the USB104 A7's Master XDC file, available through Digilent's [[https://github.com/Digilent/digilent-xdc|digilent-xdc]] repository on Github. A SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Bank 15 of the FPGA is dedicated to the Zmod port and is powered by a dedicated adjustable rail, configured by the Platform MCU as the USB104 A7 is powered on. Template constraints for the Zmod port can be found in the USB104 A7's Master XDC file, available through Digilent's [[https://github.com/Digilent/digilent-xdc|digilent-xdc]] repository on Github.
  
-Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[reference:zmod:start|Digilent Zmod]]. Demos are available for the Zmod ADC and the Zmod DAC on the USB104 A7's [[start|Resource Center]].+Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[zmod:start|Digilent Zmod]]. Demos are available for the Zmod ADC and the Zmod DAC on the USB104 A7's [[start|Resource Center]].
  
 For more information on the SYZYGY standard, see [[https://syzygyfpga.io/|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://syzygyfpga.io/|syzygyfpga.io]].