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programmable-logic:pltw-s7:reference-manual [2021/05/14 23:04] – ↷ Page moved from reference:programmable-logic:pltw-s7:reference-manual to programmable-logic:pltw-s7:reference-manual Arthur Brownprogrammable-logic:pltw-s7:reference-manual [2023/02/09 13:01] (current) – external edit 127.0.0.1
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-====== Features ======+===== Features =====
  
   * **Xilinx Spartan-7 FPGA (XC7S25-1CSGA225C)**   * **Xilinx Spartan-7 FPGA (XC7S25-1CSGA225C)**
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-====== Software Support ======+===== Software Support =====
  
 The PLTW S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2018.1 and newer. It is supported under the free WebPACK™ installation option, which does not require a license, so designs can be implemented at no additional cost. This free installation includes the ability to create MicroBlaze™ soft-core processor designs. The PLTW S7 is fully compatible with the high-performance Vivado ® Design Suite versions 2018.1 and newer. It is supported under the free WebPACK™ installation option, which does not require a license, so designs can be implemented at no additional cost. This free installation includes the ability to create MicroBlaze™ soft-core processor designs.
  
-The PLTW S7 can be used with Vivado 2017.4, but WebPACK installations of this version of Vivado may not contain the device files for the Spartan-7 FPGA used on the PLTW S7. See this [[https://www.xilinx.com/support/answers/70505.html|Xilinx Answer Record]] for more information, and for a solution.+The PLTW S7 can be used with Vivado 2017.4, but WebPACK installations of this version of Vivado may not contain the device files for the Spartan-7 FPGA used on the PLTW S7. See this [[https://support.xilinx.com/s/article/70505|Xilinx Answer Record]] for more information, and for a solution.
  
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-====== Functional Description ======+===== Functional Description =====
  
 ===== 1 Power Supplies ===== ===== 1 Power Supplies =====
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 FPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25L3233F). The FPGA will automatically read a configuration file from this device at power on. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving about 69% of the flash device (or ~2.8 MB) available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the onboard block memory. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK. FPGA Configuration files can be written to the Quad-SPI Flash (Macronix part number MX25L3233F). The FPGA will automatically read a configuration file from this device at power on. A Spartan-7 25T configuration file requires 9,935,224 bits of memory, leaving about 69% of the flash device (or ~2.8 MB) available for user data. A common use for this extra memory is to store MicroBlaze programs too big to fit in the onboard block memory. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into the bitstream, and then program the bitstream and large MicroBlaze program into the Quad SPI Flash using Xilinx SDK.
  
-The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. Refer to [[https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf|Xilinx's product guide]] for this core to learn more about using it, or to [[http://www.macronix.com/Lists/Datasheet/Attachments/6744/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf|Macronix's datasheet]] for the flash device to learn how to implement a custom controller. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O.+The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI IP core can be used to read/write the flash in a MicroBlaze design. Refer to [[https://docs.xilinx.com/v/u/en-US/pg153-axi-quad-spi|Xilinx's product guide]] for this core to learn more about using it, or to [[http://www.macronix.com/Lists/Datasheet/Attachments/6744/MX25L3233F,%203V,%2032Mb,%20v1.6.pdf|Macronix's datasheet]] for the flash device to learn how to implement a custom controller. All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O.
  
 {{ :reference:programmable-logic:cmod-s7:cmod-s7-flash.png?400 |Figure 3.1 Flash Interface}} {{ :reference:programmable-logic:cmod-s7:cmod-s7-flash.png?400 |Figure 3.1 Flash Interface}}
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 ===== 4 Oscillators/Clocks ===== ===== 4 Oscillators/Clocks =====
  
-The PLTW S7 includes a 12 MHz crystal oscillator connected to pin M9 (an MRCC input on bank 14). This clock is intended to be used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. The 12 MHz input clock cannot directly drive a PLL because they have a minimum input frequency of 19 MHz. Some rules restrict which MMCMs and PLLs may be driven by the 12 MHz input clock. For a full description of these rules and of the capabilities of the Spartan-7 clocking resources, refer to [[https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|Xilinx UG472]], titled “7 Series FPGAs Clocking Resources User Guide”.+The PLTW S7 includes a 12 MHz crystal oscillator connected to pin M9 (an MRCC input on bank 14). This clock is intended to be used as a general purpose system clock. The clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. The 12 MHz input clock cannot directly drive a PLL because they have a minimum input frequency of 19 MHz. Some rules restrict which MMCMs and PLLs may be driven by the 12 MHz input clock. For a full description of these rules and of the capabilities of the Spartan-7 clocking resources, refer to [[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|Xilinx UG472]], titled “7 Series FPGAs Clocking Resources User Guide”.
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.
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 The pins directly connected to the FPGA can be used as general purpose inputs or outputs. Each of these pins is connected to the FPGA via a 620 Ohm series resistor. The series resistors prevent short circuits that can occur if a user accidentally drives a signal that is supposed to be used as an input. In combination with Schottky diodes placed between the 3.3V power rail and each digital pin, these resistors also help to protect the FPGA from high input voltages. The downside to this added protection is that the maximum switching speed of these signals is limited to 5 MHz. These pins support input voltages of up to 5.5V. The pins directly connected to the FPGA can be used as general purpose inputs or outputs. Each of these pins is connected to the FPGA via a 620 Ohm series resistor. The series resistors prevent short circuits that can occur if a user accidentally drives a signal that is supposed to be used as an input. In combination with Schottky diodes placed between the 3.3V power rail and each digital pin, these resistors also help to protect the FPGA from high input voltages. The downside to this added protection is that the maximum switching speed of these signals is limited to 5 MHz. These pins support input voltages of up to 5.5V.
  
-For more information on the electrical characteristics of these pins, please see Xilinx's [[https://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf|Spartan-7 Datasheet]].+For more information on the electrical characteristics of these pins, please see Xilinx's [[https://docs.xilinx.com/v/u/en-US/ds189-spartan-7-data-sheet|Spartan-7 Datasheet]].
  
 ==== 7.2 Analog Inputs ==== ==== 7.2 Analog Inputs ====
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 //Figure 7.2.1 Analog Input Circuit// //Figure 7.2.1 Analog Input Circuit//
  
-The XADC core within the Spartan-7 is a dual-channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by either of the two auxiliary analog inputs to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration port (DRP). The DRP also provides access to a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to [[https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf|Xilinx UG480]], titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". A demo that uses the XADC core is available on the [[start|PLTW S7 Resource Center]]+The XADC core within the Spartan-7 is a dual-channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by either of the two auxiliary analog inputs to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration port (DRP). The DRP also provides access to a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|Xilinx UG480]], titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". A demo that uses the XADC core is available on the [[start|PLTW S7 Resource Center]]
  
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