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programmable-logic:nexys-a7:reference-manual [2023/05/19 19:13] – Arthur Brownprogrammable-logic:nexys-a7:reference-manual [2023/06/22 21:20] (current) – Arthur Brown
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 | **Setting**                                           | **Value**                   | | **Setting**                                           | **Value**                   |
 | Memory type                                           | DDR2 SDRAM                  | | Memory type                                           | DDR2 SDRAM                  |
-| Max. clock period                                     | 3000ps (667Mbps data rate)  | +| Max. clock period                                     | 3000ps (667 MT/s data rate)  | 
-| Recommended clock period (for easy clock generation)  | 3077ps (650Mbps data rate)  |+| Recommended clock period (for easy clock generation)  | 3077ps (650 MT/s data rate)  |
 | Memory part                                           | MT47H64M16HR-25E            | | Memory part                                           | MT47H64M16HR-25E            |
 | Data width                                            | 16                          | | Data width                                            | 16                          |
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 | Internal termination impedance                        | 50ohms                      | | Internal termination impedance                        | 50ohms                      |
  
-Although the FPGA, memory IC, and the board itself are capable of the maximum data rate of 667Mbps, the limitations in the clock generation primitives restrict the clock frequencies that can be generated from the 100 MHz system clock. Thus, for simplicity, the next highest data rate of 650Mbps is recommended.+Although the FPGA, memory IC, and the board itself are capable of the maximum data rate of 667 MT/s, the limitations in the clock generation primitives restrict the clock frequencies that can be generated from the 100 MHz system clock. Thus, for simplicity, the next highest data rate of 650 MT/s is recommended.
  
 The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience, an importable UCF file is provided on the Digilent website to speed up the process.