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programmable-logic:nexys-a7:demos:dma-audio [2022/09/12 12:47] – changed forum.digilentinc.com to forum.digilent.com Jeffreyprogrammable-logic:nexys-a7:demos:dma-audio [2023/08/24 23:28] (current) – Arthur Brown
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 +====== Nexys A7 DMA Audio Demo ======
  
 +<WRAP todo important>
 +== Under Construction ==
 +</WRAP>
 +
 +{{:reference:programmable-logic:nexys-a7:nexys-a7-top-600.png?400|}}
 +----
 +===== Description =====
 +
 +This project demonstrates how to stream data in and out of the Nexys A7's RAM.
 +
 +To use this demo, the Nexys A7-100T must be connected to a computer over MicroUSB, which must be running a serial terminal with a baud rate of 230400.
 +
 +Review statements printed over USB-UART for more information on how to operate this demo. FIXME pull anything from here into this document.
 +
 +This demo is a work in progress, and as such only supports WAV files with 96KHz sample rates. 8-bit and 16-bit audio is supported, but 16-bit data is truncated down to 8 bits, which may result in poor sound quality.
 +
 +----
 +===== Inventory =====
 +
 +  * Nexys A7 with a MicroUSB Programming Cable
 +  * Vivado and Vitis installations compatible with the latest release of this demo (2020.1)
 +    * //See [[programmable-logic:guides:installing-vivado-and-vitis|Installing Vivado, Vitis, and Digilent Board Files]] for installation instructions.//
 +  * Serial Terminal application to receive messages printed by the demo
 +    * //See [[programmable-logic:guides:serial-terminals:start]] for more information.//
 +  * Headphones or Speakers with 3.5mm Audio Jack
 +
 +----
 +===== Download and Usage Instructions =====
 +
 +The following releases of this demo can be used with instructions found in the corresponding READMEs in order to run the demo.
 +
 +Releases are only compatible with the version of the Xilinx tools specified in the release version number. In addition, releases are only compatible with the specified variant of the board. For example, the v2020.1-1 release for Nexys A7-100T can only be used with Vivado and Vitis 2020.1 and Nexys A7-100T variant of the board.
 +
 +The latest release version for this demo is highlighted in green.
 +
 +**Note:** //Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.//
 +
 +^ Board Variant  ^ Release Tag  ^ Release Downloads  ^ Setup Instructions  |
 +| Nexys A7-100T  | @#C0EEBD: 100T/DMA-Audio/2020.1-1  | {{https://github.com/Digilent/Nexys-A7/releases/download/100T/DMA-Audio/2020.1-1/Nexys-A7-100T-DMA-Audio-hw.xpr.zip}} \\ {{https://github.com/Digilent/Nexys-A7/releases/download/100T/DMA-Audio/2020.1-1/Nexys-A7-100T-DMA-Audio-sw.ide.zip}}  | See //Using the Latest Release//, below  |
 +| Nexys A7-50T   | @#C0EEBD: 50T/DMA-Audio/2020.1-1   | {{https://github.com/Digilent/Nexys-A7/releases/download/50T/DMA-Audio/2020.1-1/Nexys-A7-50T-DMA-Audio-hw.xpr.zip}}   \\ {{https://github.com/Digilent/Nexys-A7/releases/download/50T/DMA-Audio/2020.1-1/Nexys-A7-50T-DMA-Audio-sw.ide.zip}}    | See //Using the Latest Release//, below  |
 +| Nexys A7-100T  | v2018.2-1                          | [[https://github.com/Digilent/Nexys-A7-100T-DMA-Audio/releases/tag/v2018.2-1|Release ZIP Downloads]] | [[https://github.com/Digilent/Nexys-A7-100T-DMA-Audio/tree/v2018.2-1|Github README]]  |
 +| Nexys A7-50T   | v2018.2-1                          | [[https://github.com/Digilent/Nexys-A7-50T-DMA-Audio/releases/tag/v2018.2-1|Release ZIP Downloads]] | [[https://github.com/Digilent/Nexys-A7-50T-DMA-Audio/tree/v2018.2-1|Github README]]  |
 +
 +**Note for Advanced Users:** //GitHub sources for this demo can be found in the [[https://github.com/digilent/nexys-a7/tree/100T/DMA-Audio/master|100T/DMA-Audio/master]] and [[https://github.com/digilent/nexys-a7/tree/50T/DMA-Audio/master|50T/DMA-Audio/master]] branches of the Nexys-A7 repository. Further documentation on the structure of this repository can be found on this wiki's [[programmable-logic:documents:git]] page.//
 +----
 +Instructions on the use of the latest release can be found in this dropdown:
 +
 +--> Using the Latest Release #^
 +<WRAP group>
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_no_build&noheader}}
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_workaround_before_programming&noheader}}
 +
 +--> Build a Vitis Application #
 +<WRAP group>
 +{{page>programmable-logic:guides:vitis-build-software&noheader}}
 +</WRAP>
 +<--
 +
 +--> Set up the Nexys A7 #
 +
 +Plug the microUSB programming cable into the Nexys A7's PROG/UART port and the headphones or speakers into the MONO AUDIO OUT port.
 +
 +----
 +<--
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_programming&noheader}}
 +
 +At this point, the demo is now running on your board. Refer to the [[#description|Description]] section of this document for more information on what it does.
 +----
 +Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.
 +----
 +{{page>programmable-logic:guides:using-github-releases#baremetal_update_specification&noheader}}
 +
 +
 +</WRAP>
 +<--
 +
 +----
 +===== Additional Resources =====
 +
 +All materials related to the use of the Nexys A7 can be found on its [[..:start|Resource Center]].
 +
 +For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see [[programmable-logic:guides:getting-started-with-ipi]]. Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.
 +
 +For technical support, please visit the [[https://forum.digilent.com/forum/4-fpga/|FPGA]] section of the Digilent Forum.
 +
 +----
 +<code>{{tag>project nexys-a7}}</code>