Differences
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| Both sides previous revisionPrevious revision | |||
| programmable-logic:nexys-4-ddr:start [2022/03/07 22:48] – cut buy button Arthur Brown | programmable-logic:nexys-4-ddr:start [2022/09/12 19:22] (current) – changed forum.digilentinc.com to forum.digilent.com, and some type-o's Jeffrey | ||
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| Line 4: | Line 4: | ||
| {{Digilent Infobox | {{Digilent Infobox | ||
| | Manual = [[reference-manual]] | | Manual = [[reference-manual]] | ||
| - | | Support = https:// | + | | Support = https:// |
| | Title = Nexys 4 DDR | | Title = Nexys 4 DDR | ||
| | Subtitle = Artix-7 FPGA | | Subtitle = Artix-7 FPGA | ||
| Line 16: | Line 16: | ||
| | Clock Tiles = 6 (each with PLL) | | Clock Tiles = 6 (each with PLL) | ||
| | DSP Slices = 240 | | DSP Slices = 240 | ||
| - | | Internal clock = 450MHz+ | + | | Internal clock = 450 MHz+ |
| | DDR2 = 128 MiB | | DDR2 = 128 MiB | ||
| | Cellular RAM = 16MB | | Cellular RAM = 16MB | ||
| Line 33: | Line 33: | ||
| | Tri-color LEDs = 2 | | Tri-color LEDs = 2 | ||
| | Header = Electrical | | Header = Electrical | ||
| - | | Power = USB \\ 5V (2.5mm coaxial) supply | + | | Power = USB \\ 5 V (2.5 mm coaxial) supply |
| - | | Logic Level = 3.3V | + | | Logic Level = 3.3 V |
| | Header = Physical | | Header = Physical | ||
| | Width = 4.3 in | | Width = 4.3 in | ||