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programmable-logic:guides:getting-started-with-ipi [2021/06/04 17:40] – [Inventory] Arthur Brown | programmable-logic:guides:getting-started-with-ipi [2023/12/04 23:47] (current) – [Requirements] Arthur Brown | ||
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~~TechArticle~~ | ~~TechArticle~~ | ||
- | ====== Getting Started with Vivado | + | ====== Getting Started with Vivado and Vitis for Baremetal Software Projects |
- | /* Note to maintainers, | + | /* Note to maintainers, |
===== Overview ===== | ===== Overview ===== | ||
- | This guide will work you through the process of setting up a project in Vivado and Vitis. A simple hardware design including a processor with several AXI GPIO peripherals connected to buttons and LEDs will be created. This design will then be exported to the Vitis IDE, and a software project will be created and run which polls the buttons and writes to the LEDs. | + | This guide will work you through the process of setting up a project in Vivado and Vitis. A simple hardware design including a processor with several AXI GPIO peripherals connected to buttons and LEDs will be created. This design will then be exported to the Vitis IDE, and a baremetal |
- | **Note:** // | ||
---- | ---- | ||
- | ===== Inventory | + | ===== Requirements |
* A Digilent FPGA Development Board | * A Digilent FPGA Development Board | ||
* USB Programming cables, USB UART cables, and Power Supply, as required by the board. | * USB Programming cables, USB UART cables, and Power Supply, as required by the board. | ||
+ | * **Note:** //The Genesys ZU is not supported by this guide, as it uses a Zynq Ultrascale+ MPSoC part, and requires additional configuration of its bootloader. Please see the getting started info specific to it, found on its [[programmable-logic/ | ||
* Vivado and Vitis installations | * Vivado and Vitis installations | ||
- | * See [[programmable-logic: | + | * See [[programmable-logic: |
- | * **Important!** At the time of writing, if using Microblaze, it is recommended to use an alternate version of the board files which better support the DDR memory present | + | * You also need the board files for your board. This guide is intended for use with the board files available from Digilent' |
+ | |||
+ | <WRAP round info> | ||
+ | Screenshots presented in this guide may not have been taken with your version of the tools. The workflow process presented here has been verified in Vivado and Vitis 2022.1. | ||
+ | |||
+ | Substantial UI changes in Vitis 2023.2 have changed much of the specifics of how to create a project in that tool. For a detailed rundown of changes, check out Adam Taylor' | ||
+ | |||
+ | If you are using a version of Vivado that includes Xilinx SDK (2019.1 or older), check out [[vivado/getting-started-with-ipi/ | ||
+ | </ | ||
+ | |||
+ | <WRAP round info> | ||
+ | The user Viktor Nikolov posted a tutorial on the Digilent Forum with an alternate architecture for clocking the DDR interface for Digilent | ||
+ | </ | ||
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{{page> | {{page> | ||
- | It's time to program | + | It's time to program your Digilent |
---- | ---- | ||
{{page> | {{page> | ||
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For more guides and demos for your board, return to the device' | For more guides and demos for your board, return to the device' | ||
- | For technical support, please visit the [[https:// | + | For technical support, please visit the [[https:// |