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programmable-logic:genesys-zu:demos:hello-world [2022/09/12 12:37] – changed forum.digilentinc.com to forum.digilent.com Jeffrey | programmable-logic:genesys-zu:demos:hello-world [2023/08/24 23:16] (current) – Move to direct file links for downloads Arthur Brown | ||
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+ | ====== Genesys ZU Hello World Demo ====== | ||
+ | <WRAP todo important> | ||
+ | == Under Construction == | ||
+ | </ | ||
+ | |||
+ | ---- | ||
+ | ===== Description ===== | ||
+ | This project is a simple demo that configures the Zynq Ultrascale+ MPSoc with the given board file, and outputs "Hello World" on the serial terminal. | ||
+ | ---- | ||
+ | ===== Inventory ===== | ||
+ | |||
+ | * Genesys ZU-5EV with a MicroUSB Programming Cable and a Power Supply | ||
+ | * Vivado installation compatible with the latest release of this demo (2023.1) | ||
+ | * //See [[programmable-logic: | ||
+ | |||
+ | ---- | ||
+ | ===== Download and Usage Instructions ===== | ||
+ | |||
+ | First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a //release tag//). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged " | ||
+ | |||
+ | The latest release version for this demo is highlighted in green. | ||
+ | |||
+ | **Note:** //Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.// | ||
+ | |||
+ | ^ Board Variant | ||
+ | | Genesys ZU-5EV | ||
+ | | Genesys ZU-3EG | ||
+ | | Genesys ZU-5EV | ||
+ | | Genesys ZU-5EV | ||
+ | | Genesys ZU-5EV | ||
+ | | Genesys ZU-3EG | ||
+ | | Genesys ZU-5EV | ||
+ | |||
+ | **Note for Advanced Users:** //GitHub sources for this demo can be found in the [[https:// | ||
+ | ---- | ||
+ | Instructions on the use of the latest release can be found in this dropdown: | ||
+ | |||
+ | --> Using the Latest Release #^ | ||
+ | <WRAP group> | ||
+ | |||
+ | **Note:** //This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.// | ||
+ | |||
+ | **Important: | ||
+ | |||
+ | First, download the ' | ||
+ | |||
+ | **Note:** //Unlike with Vivado XPR archives, do NOT extract the Vitis project archive (' | ||
+ | ---- | ||
+ | --> Import Vitis Projects from a Release # | ||
+ | <WRAP group> | ||
+ | {{page> | ||
+ | |||
+ | <WRAP group> <WRAP column half> | ||
+ | With Vitis open, click the **Import Project** button to import projects from a //Vitis project exported zip file//. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | With Vitis open, please make sure that **Vitis project exported zip file** button is selected, then click Next and navigate to and select the IDE zip file you downloaded. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Make sure each project in the archive is checked, then click **Finish** to import them into your workspace. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | After the import, you should see all the sources into the workspace. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | </ | ||
+ | <-- | ||
+ | |||
+ | --> Build a Vitis Application # | ||
+ | **Note:** //Depending the case, //*// stays either for 3EG or 5EV.// | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Double-click on //*_boot// in order to see all the sub-directories, | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Without change anything, click //OK//. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | A warning message will pop-up saying that all the build configurations will be cleaned. This is what we actually want to happen, so click // | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Right-click on *_fsbl.prj and select // | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Right-click on *_boot project and select //Build Project// | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | You can see the progress on the bottom-right side of the screen. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | After the build, an error should be reported into the console regarding the missing platform fsbl.elf file. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Browse for the // | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | |||
+ | <WRAP group> <WRAP column half> | ||
+ | Next we have to build the *_master project, and for that we have to set the path for the lscript.ld. Right-click on *_master.prj and select // | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | Right-click on *_master_system project and select //Build Project//. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | The build should take a couple of seconds. | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <-- | ||
+ | |||
+ | --> Set up the Genesys ZU # | ||
+ | |||
+ | --> Set up the Genesys ZU-5EV# | ||
+ | Plug the microUSB programming cable into the Genesys ZU-5EV' | ||
+ | <-- | ||
+ | |||
+ | |||
+ | --> Set up the Genesys ZU-3EG# | ||
+ | Plug the microUSB programming cable into the Genesys ZU-3EG' | ||
+ | <-- | ||
+ | <-- | ||
+ | --> Launch the Vitis Baremetal Software Application# | ||
+ | |||
+ | <WRAP group> <WRAP column half> | ||
+ | First, many applications require that a serial console is connected to the board, so that standard output (from print statements) can be viewed. For this purpose, a serial terminal should be used. Use a serial terminal application to connect to the board' | ||
+ | |||
+ | **Note:** //While Vitis has a built in serial terminal included in its Debug view, it sends characters to a board on a line-by-line basis. Some software examples require the use of character-by-character reception of data. [[https:// | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | ---- | ||
+ | <WRAP group> <WRAP column half> | ||
+ | In the // | ||
+ | |||
+ | **Note:** //Once the project has been run at least once, you can use the green run button ({{: | ||
+ | </ | ||
+ | {{ : | ||
+ | </ | ||
+ | <-- | ||
+ | ---- | ||
+ | At this point, the demo is now running on your board. Refer to the [[# | ||
+ | ---- | ||
+ | Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis. | ||
+ | ---- | ||
+ | |||
+ | {{page> | ||
+ | |||
+ | <WRAP center round important 100%> | ||
+ | After every Platform Specification update, please make sure you follow these steps, to ensure the Platform Specification changes are correctly applied to your software project: | ||
+ | - Open [3eg|5ev]_hw_pf -> platform.spr and make sure the FSBL file location is correctly set ([..]\ws\[3eg|5ev]_fsbl\Release\[3eg|5ev]_fsbl.elf). | ||
+ | - Right click on [3eg|5ev]_hw_pf and select Update Hardware Specification. Make sure the path is correct ([..]/ | ||
+ | - Right click on [3eg|5ev]_hw_pf and select Build Project. | ||
+ | - Right click on [3eg|5ev]_boot and select Build Project. | ||
+ | - Genesys ZU workspaces externalize FSBL into a stand-alone application project to work around the wrong FSBL BSP optimization flag bug when it is generated as part of a hardware platform project. The ZynqMP FSBL is a template project that gets recreated upon checkout with local copies of sources from the local " | ||
+ | - Right click on [3eg|5ev]_boot and select Build Project. | ||
+ | - If you still encounter an error saying that fsbl.elf is not found, copy the [..]\ws\[3eg|5ev]_fsbl\Release\[3eg|5ev]_fsbl.elf file to [..]\ws\[3eg|5ev]_hw_pf\export\[3eg|5ev]_hw_pf\sw\[3eg|5ev]_hw_pf\boot\, | ||
+ | - Right click on [3eg|5ev]_master_system and select Build Project. | ||
+ | </ | ||
+ | |||
+ | </ | ||
+ | <-- | ||
+ | ---- | ||
+ | ===== Functionality ===== | ||
+ | |||
+ | ==== 1. Serial Terminal ==== | ||
+ | |||
+ | The "Hello World" and " | ||
+ | |||
+ | |||
+ | ===== Additional Resources ===== | ||
+ | |||
+ | All materials related to the use of the Genesys ZU can be found on its [[learn: | ||
+ | |||
+ | For a walkthrough of the process of creating a simple HDL project in Vivado, see [[programmable-logic: | ||
+ | |||
+ | For technical support, please visit the [[https:// | ||
+ | |||
+ | {{tag> |