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programmable-logic:genesys-2:reference-manual [2021/09/29 20:10] – Arthur Brownprogrammable-logic:genesys-2:reference-manual [2024/02/14 21:14] (current) – [7. Ethernet PHY] James Colvin
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 === Download This Reference Manual === === Download This Reference Manual ===
-  * {{ :reference:programmable-logic:genesys-2:genesys2_rm.pdf |Genesys 2 PDF}}+  * {{ :reference:programmable-logic:genesys-2:genesys2_rm.pdf |Genesys 2 PDF (not up-to-date, use online version instead)}}
  
  
-====== Features ======+===== Features =====
 ---- ----
  
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   * On-chip analog-to-digital converter (XADC)   * On-chip analog-to-digital converter (XADC)
   * Up to 10.3125Gbps gigabit transceivers   * Up to 10.3125Gbps gigabit transceivers
-  * 1800Mbps DDR3 data rate with 32-bit data width+  * 1800 MT/s DDR3 data rate with 32-bit data width
   * Commercial -2 speed grade   * Commercial -2 speed grade
   * Fully bonded  400-pin FMC HPC connector   * Fully bonded  400-pin FMC HPC connector
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   * HDMI Sink and HDMI Source    * HDMI Sink and HDMI Source 
   * 10/100/1000 Ethernet PHY   * 10/100/1000 Ethernet PHY
-  * 1GiB 1800Mt/s on-board DDR3+  * 1GiB 1800 MT/s on-board DDR3
   * USB 2.0 Host/Device/OTG PHY   * USB 2.0 Host/Device/OTG PHY
   * Digilent Adept USB port for programming and data   * Digilent Adept USB port for programming and data
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 The Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash or the on-board USB-JTAG programmer circuit. The Genesys 2 can be programmed from various sources, like USB thumb drive, microSD, the on-board non-volatile Flash or the on-board USB-JTAG programmer circuit.
- 
-The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset. Included in the box is a voucher that unlocks the Design Edition of Vivado that is device-locked to the Genesys 2. This allows designs to be implemented straight out of the box at no additional cost. The Design Edition of Vivado also unlocks the Logic Analyzer tool and still includes the ability to create Microblaze soft-core processor projects.  
  
 {{ :genesys2:genesys2_callout.png?nolink |}} {{ :genesys2:genesys2_callout.png?nolink |}}
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 Table 1. Genesys 2 features and connectors.  Table 1. Genesys 2 features and connectors. 
- 
  
 ---- ----
 +===== Software Support =====
  
-===== 1. Quick-start =====+The Genesys 2 is [[https://www.xilinx.com/products/design-tools/vivado/vivado-ml.html#architecture|compatible]] with the Xilinx Vivado ML Enterprise Edition (formerly Vivado® Design Suite) as well as the older ISE toolset. The Kintex-7 325T part on the Genesys 2 is not supported by Vivado ML Standard Edition (formerly Vivado WebPACK™). Included in the box is a voucher that unlocks the Enterprise Edition license (formerly Design Edition) of Vivado that is device-locked to the Genesys 2. This allows designs to be implemented straight out of the box at no additional cost. 
 + 
 +--> Voucher Redeeming Steps # 
 +  - Access https://www.xilinx.com/getlicense and log-in/register with Xilinx. 
 +  - Enter the 25-character voucher code and click "Redeem Now". 
 +  - Confirm the name "OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher" and redeem it for your account. 
 +  - This being a node-locked license, add a host by and ID (MAC address for ex.) and accept the terms and conditions. 
 +  - Import the *.lic file sent over e-mail in Vivado License Manager. 
 + 
 +{{Digilent Image Gallery  
 +| image = {{ :programmable-logic:genesys-2:license_voucher1.png |}} 
 +| image = {{ :programmable-logic:genesys-2:license_voucher2.png |}} 
 +| image = {{ :programmable-logic:genesys-2:license_voucher3.png |}} 
 +}} 
 + 
 +<-- 
 + 
 +Digilent provides a variety of demos for the Genesys 2, demonstrating use of many of its features. The table in the dropdown below details each of these demos, which features they use, and the latest version of Vivado and Xilinx SDK that they support. Additionally, several guides and tutorials can be found on the [[start|Genesys 2 Resource Center]], including a programming guide, an introduction to setting up a MicroBlaze server with ethernet, and more. 
 + 
 +**Important:** Several of these demos and guides require licenses. In particular, materials using the Gigabit Ethernet PHY and DisplayPort connectors require licenses for the TEMAC and DisplayPort IP licenses from Xilinx. 
 + 
 +Despite the fact that the version of the Out-of-Box demo that is programmed into the Genesys 2's flash during manufacturing correctly drives DisplayPort, due to changes made to the DisplayPort IP made between Vivado 2014.4 (the original version the demo was written in) and 2015.4 (targeted by the first GitHub release of the demo), DisplayPort is not supported by the out-of-box demo. 
 + 
 +**Note:** The source files for the original version of the Out-of-Box demo created for 2014.4, with a functioning DisplayPort implementation, were posted on the Digilent Forum here: [[https://forum.digilent.com/topic/19560-error-importing-genesys2-oob-project-sdk/#comment-53714]] 
 + 
 +--> Genesys 2 Supported Projects # 
 +|<100% 20% 10% 10% 10% 10% 10% 10%>| 
 +^ ^  [[programmable-logic:genesys-2:demos:dma-audio|DMA Audio]]  ^  [[programmable-logic:genesys-2:demos:hdmi|HDMI]]  ^  [[programmable-logic:genesys-2:demos:keyboard|Keyboard]]  ^  [[programmable-logic:genesys-2:demos:oled|OLED]]  ^  [[programmable-logic:genesys-2:demos:oob|Out-of-Box]]  ^  [[programmable-logic:genesys-2:demos:usb-device|USB Device]]  ^ 
 +^ Supported Version of Vivado and SDK  ^  2016.4  ^  2016.4  ^  2016.4  ^  2016.4  ^  2015.4  ^  2015.4  ^ 
 +^  Supported Features  ^  ^^^^^^ 
 +^  8 User Switches                                 |  No             |  No             |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  8 User LEDs                                     |  No             |  No             |  No             |  @#A9E091: Yes  |  @#A9E091: Yes  |  No             | 
 +^  6 User Push Buttons                             |  @#A9E091: Yes  |  No             |  No             |  @#A9E091: Yes  |  @#A9E091: Yes  |  @#A9E091: Yes  | 
 +^  128×32 Monochrome OLED Display                  |  No             |  No             |  No             |  @#A9E091: Yes  |  @#A9E091: Yes  |  No             | 
 +^  USB-UART Bridge                                 |  @#A9E091: Yes  |  @#A9E091: Yes  |  @#A9E091: Yes  |  No             |  @#A9E091: Yes  |  @#A9E091: Yes  | 
 +^  Fully Bonded 400-pin FMC HPC Connector          |  No             |  No             |  No             |  No             |  No             |  No             | 
 +^  Micro SD Card Connector                         |  No             |  No             |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  HDMI Sink and HDMI Source                       |  No             |  @#A9E091: Yes  |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  VGA Connector                                   |  No             |  No             |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  Two four-lane DisplayPort Connectors            |  No             |  No             |  No             |  No             |  No [(The Out-of-Box demo's support for DisplayPort is nonfunctional in sources released on GitHub.)]  |  No             | 
 +^  Audio Codec w/ Four 3.5mm Jacks                 |  @#A9E091: Yes  |  No             |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  10/100/1000 Ethernet PHY                        |  No             |  No             |  No             |  No             |  @#A9E091: Yes  |  No             | 
 +^  1 GiB 1800 MT/s DDR3 Memory                     |  @#A9E091: Yes  |  @#A9E091: Yes  |  No             |  No             |  @#A9E091: Yes  |  @#A9E091: Yes  | 
 +^  Serial Flash                                    |  No             |  No             |  No             |  No             |  No             |  No             | 
 +^  Five Pmod Ports                                 |  No             |  No             |  No             |  No             |  No             |  No             | 
 +^  Pmod for XADC Signals                           |  No             |  No             |  No             |  No             |  No             |  No             | 
 +^  USB HID Host                                    |  No             |  No             |  @#A9E091: Yes  |  No             |  No             |  No             | 
 +^  USB 2.0 Host/Device/OTG PHY                     |  No             |  No             |  No             |  No             |  No             |  @#A9E091: Yes  | 
 +^  PC - FPGA Data Transfer Interfaces (DPTI/DSPI)  |  No             |  No             |  No             |  No             |  No             |  No             | 
 + 
 +~~REFNOTES~~ 
 + 
 +<-- 
 + 
 +The Genesys 2 can be used with newer versions of Vivado, Xilinx SDK, and Vitis, and the materials described above may be useful in getting projects set up, however, there may be substantial differences in the Xilinx IP that are used in these demos that have been added over time. For the most confidence that these features will work as intended with the minimum amount of additional setup work, Digilent recommends the use of these materials in the version they were created in. Digilent does not plan on updating these demos into any newer version of the tools. 
 + 
 +---- 
 +===== Functional Description ===== 
 +==== 1. Quick-start ====
  
 The Genesys 2 comes with an out-of-box demo design that gets loaded from the on-board QSPI flash. It exercises most of the on-board peripherals. Just power the board with the included 12V wall supply, flick the power switch, wait for the design to fully load and explore the following features: The Genesys 2 comes with an out-of-box demo design that gets loaded from the on-board QSPI flash. It exercises most of the on-board peripherals. Just power the board with the included 12V wall supply, flick the power switch, wait for the design to fully load and explore the following features:
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 ---- ----
  
-===== 2. Power Supplies =====+==== 2. Power Supplies ====
  
 The Genesys 2 board can receive power from an external power supply through the center-positive barrel jack (J27). The external supply voltage must be 12 V ±5 %. The Genesys 2 cannot be powered from the USB bus.  The Genesys 2 board can receive power from an external power supply through the center-positive barrel jack (J27). The external supply voltage must be 12 V ±5 %. The Genesys 2 cannot be powered from the USB bus. 
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 | 1.5 V             | DDR3 and FPGA I/O                                                              | IC32: LTC3618    | 2 A / 0.7 A            | | 1.5 V             | DDR3 and FPGA I/O                                                              | IC32: LTC3618    | 2 A / 0.7 A            |
 | 0.75V             | DDR3 termination, reference                                                    | IC32: LTC3618    | 2 A                    | | 0.75V             | DDR3 termination, reference                                                    | IC32: LTC3618    | 2 A                    |
-| 2.0 V             | FPGA Auxiliary I/O for memory high data rates((See the 7-Series FPGAs SelectIO Resources User Guide ([[http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf|ug471]]) for details.))                                  | IC38: LT1762     | 150 mA                 |+| 2.0 V             | FPGA Auxiliary I/O for memory high data rates((See the 7-Series FPGAs SelectIO Resources User Guide ([[https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO|ug471]]) for details.))                                  | IC38: LT1762     | 150 mA                 |
 | VADJ (1.2-3.3 V)  | User I/O, FMC and FPGA I/O                                                     | IC37: LTM4618    | 5A                     | | VADJ (1.2-3.3 V)  | User I/O, FMC and FPGA I/O                                                     | IC37: LTM4618    | 5A                     |
 | 3.3 V             | Audio analog supply                                                            | IC12: LT1761     | 100 mA                 | | 3.3 V             | Audio analog supply                                                            | IC12: LT1761     | 100 mA                 |
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 ---- ----
  
-===== 3. Power Monitoring =====+==== 3. Power Monitoring ====
  
 I<sup>2</sup>C-interfaced monitoring circuits, INA219 from Texas Instruments, are available on the main power rails. These allow real-time voltage, current, and power readings in the FPGA. Six such circuits share the same I<sup>2</sup>C bus with different slave addresses. These are summarized in Table 3, along with recommended configuration values. I<sup>2</sup>C-interfaced monitoring circuits, INA219 from Texas Instruments, are available on the main power rails. These allow real-time voltage, current, and power readings in the FPGA. Six such circuits share the same I<sup>2</sup>C bus with different slave addresses. These are summarized in Table 3, along with recommended configuration values.
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 ---- ----
  
-===== 4. Fan =====+==== 4. Fan ====
  
 The Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan is powered from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN_EN” signal. Pulling the signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default. Feedback is obtained on the “FAN_TACH” signal. This generates a pulse with a frequency proportional to the rotation speed of the fan. Each rotation generates four pulses on “FAN_TACH”. The period of these pulses shortens with higher rotation speed and lengthens at slower speeds. The Genesys 2 comes with a fan and a secondary heat sink pre-installed on the FPGA package heat sink. The fan is powered from the external 12V DC supply rail and controlled by the FPGA. Control is done by the “FAN_EN” signal. Pulling the signal high from the FPGA opens the transistor driving the fan. This pin is pulled high by default. Feedback is obtained on the “FAN_TACH” signal. This generates a pulse with a frequency proportional to the rotation speed of the fan. Each rotation generates four pulses on “FAN_TACH”. The period of these pulses shortens with higher rotation speed and lengthens at slower speeds.
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 ---- ----
  
-===== 5. FPGA Configuration =====+==== 5. FPGA Configuration ====
  
 After power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways: After power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of four ways:
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 The following sections provide greater detail about programming the Genesys 2 using the different methods available. The following sections provide greater detail about programming the Genesys 2 using the different methods available.
  
-==== 5.1. JTAG Programming ====+=== 5.1. JTAG Programming ===
  
 The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2, attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on, regardless of what the mode jumper (JP5) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs. The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J17) or an external JTAG programmer, such as the Digilent JTAG HS2, attached to port J19. You can perform JTAG programming at any time after the Genesys 2 has been powered on, regardless of what the mode jumper (JP5) is set to. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Setting the mode jumper to the JTAG setting is useful to prevent the FPGA from being configured from any other bitstream source until a JTAG programming occurs.
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 JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Labtools version of Vivado.  JTAG programming can be done using the hardware server in Vivado or the iMPACT tool included with ISE and the Labtools version of Vivado. 
  
-The [[learn/programmable-logic/tutorials/genesys-2-programming-guide/start|demonstration project]] available on the [[programmable-logic/genesys-2/start|Genesys 2 Resource Center]] provides an in-depth tutorial on how to program your board. +The [[programmable-logic:genesys-2:programming|demonstration project]] available on the [[programmable-logic/genesys-2/start|Genesys 2 Resource Center]] provides an in-depth tutorial on how to program your board. 
  
-==== 5.2. Quad-SPI Programming ====+=== 5.2. Quad-SPI Programming ===
  
 For the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream. This is called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT (ISE). First, the FPGA is programmed with a design that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting. Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events. For the FPGA to be able to configure itself from the SPI Flash, it first needs to be programmed with the bitstream. This is called indirect programming and is a two-step process controlled by Hardware Manager (Vivado) or iMPACT (ISE). First, the FPGA is programmed with a design that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting. Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.
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 Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager of Vivado. The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion. Indirect programming of the flash can be done using the iMPACT tool included with ISE or Hardware Manager of Vivado. The correct part to be set in the tools is s25fl256xxxxxx0 from the manufacturer Spansion.
  
-==== 5.3. USB Host and Micro SD Programming ====+=== 5.3. USB Host and Micro SD Programming ===
  
 You can program the FPGA from a pen drive attached to the USB-Host port (J7-top row) or a microSD card inserted into J3 by doing the following:  You can program the FPGA from a pen drive attached to the USB-Host port (J7-top row) or a microSD card inserted into J3 by doing the following: 
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 ---- ----
  
-===== 6. Memory =====+==== 6. Memory ====
  
 The Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte non-volatile serial Flash device. The DDR3 uses two 16-bit wide memory component with industry-standard interface soldered on the board resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus. The Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte non-volatile serial Flash device. The DDR3 uses two 16-bit wide memory component with industry-standard interface soldered on the board resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus.
  
-==== 6.1. DDR3 ====+=== 6.1. DDR3 ===
  
 The Genesys 2 includes two Micron MT41J256M16HA-107 DDR3 memory component creating a single rank, 32-bit wide interface. It is routed to a 1.5V-powered HP (High Performance) FPGA bank with 40 ohm controlled single-ended trace impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching. Address/Control signals are terminated using discrete resistors. The Genesys 2 includes two Micron MT41J256M16HA-107 DDR3 memory component creating a single rank, 32-bit wide interface. It is routed to a 1.5V-powered HP (High Performance) FPGA bank with 40 ohm controlled single-ended trace impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching. Address/Control signals are terminated using discrete resistors.
  
-The highest data rate supported is 1800Mbps.+The highest data rate supported is 1800 MT/s.
  
 For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3 interface. Depending on the tool used (ISE, EDK or Vivado) the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application. Table 4 below lists the MIG Wizard settings optimized for the Genesys 2. For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3 interface. Depending on the tool used (ISE, EDK or Vivado) the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application. Table 4 below lists the MIG Wizard settings optimized for the Genesys 2.
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 | Memory type                         | DDR3 SDRAM         | | Memory type                         | DDR3 SDRAM         |
 | Max. clock period                   | 1112ps (~900MHz)   | | Max. clock period                   | 1112ps (~900MHz)   |
-| Max. data rate                      | ~1800Mbps          |+| Max. data rate                      | ~1800 MT/s          |
 | Clock ratio                         | 4:1                | | Clock ratio                         | 4:1                |
 | VCCAUX_IO                           | 2.0V               | | VCCAUX_IO                           | 2.0V               |
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 The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process. The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For your convenience an importable UCF/XDC file is provided on the Digilent website to speed up the process.
  
-For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf|User Guide (ug586)]].+For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions [[https://docs.xilinx.com/v/u/2.1-English/ug586_7Series_MIS|User Guide (ug586)]].
  
-==== 6.2. Quad-SPI Flash ====+=== 6.2. Quad-SPI Flash ===
  
 Non-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written to it, and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. A Kintex-7 325T configuration file requires just over 10 MiB (mebibyte) of memory, leaving about 70% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data. Non-volatile storage is provided by a Spansion S25FL256S flash memory. FPGA configuration files can be written to it, and mode settings are available to cause the FPGA to automatically read a configuration from this device at power on. A Kintex-7 325T configuration file requires just over 10 MiB (mebibyte) of memory, leaving about 70% of the flash device available for user data. Or, if the FPGA is getting configured from another source, the whole memory can be used for custom data.
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 The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is recommended for easy access to the Flash memory. The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. All signals in the SPI bus except SCK are general-purpose user I/O pins after FPGA configuration. SCK is an exception because it remains a dedicated pin even after configuration. Access to this pin is provided through a special FPGA primitive called STARTUPE2. The AXI Quad SPI IP core is recommended for easy access to the Flash memory.
  
-**NOTE: Refer to the manufacturer’s [[http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf|datasheets]] and Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf|user guides]] for more information.**+**NOTE: Refer to the manufacturer’s [[http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf|datasheets]] and Xilinx [[https://docs.xilinx.com/v/u/en-US/ug470_7Series_Config|user guides]] for more information.**
  
 {{ :reference:programmable-logic:genesys-2:genesys2_flash.png?550 |Figure 6. Genesys 2 SPI Flash pin-out}} {{ :reference:programmable-logic:genesys-2:genesys2_flash.png?550 |Figure 6. Genesys 2 SPI Flash pin-out}}
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-===== 7. Ethernet PHY =====+==== 7. Ethernet PHY ====
  
 The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both of these signals are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA, if they are used. The reset signal (PHYRSTB) is wired to bank 12, powered at 3.3V. The connection diagram can be seen on Figure 7. The Genesys 2 board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. Bank 33 powered at 1.5V is populated with these signals. The auxiliary interrupt (INTB), power management (PMEB) signals are wired to bank 32 and powered at 1.8V. Both of these signals are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA, if they are used. The reset signal (PHYRSTB) is wired to bank 12, powered at 3.3V. The connection diagram can be seen on Figure 7.
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 On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC address pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash6. This unique identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique MAC to allow connecting several Genesys 2 boards to the same network. On an Ethernet network each node needs a unique MAC address. To this end the Genesys 2 comes with a MAC address pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash6. This unique identifier can be read with the OTP Read command (0x4B). The out-of-box Ethernet demo uses the unique MAC to allow connecting several Genesys 2 boards to the same network.
  
-A downloadable demonstration project can be found on the [[genesys2:genesys2|Genesys 2 wiki page]].+A downloadable demonstration project can be found on the [[./start|Genesys 2 Resource Center]].
  
 {{ :reference:programmable-logic:genesys-2:genesys2_ethernet.png?500 |Figure 7. Pin connections between the FPGA and the Ethernet PHY.}} {{ :reference:programmable-logic:genesys-2:genesys2_ethernet.png?500 |Figure 7. Pin connections between the FPGA and the Ethernet PHY.}}
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-===== 8. Oscillators/Clocks =====+==== 8. Oscillators/Clocks ====
  
-The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf|ug472]]) available from Xilinx.+The Genesys 2 board includes several oscillators and crystals, of which two are connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. This input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” ([[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking|ug472]]) available from Xilinx.
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools. Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado Block Design or Core Generator tools.
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-===== 9. USB UART Bridge (Serial Port) =====+==== 9. USB UART Bridge (Serial Port) ====
  
 The Genesys 2 includes an FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins. The Genesys 2 includes an FTDI FT232R USB-UART bridge (attached to connector J15) that lets you use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from Windows Update or www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) with no handshake signals. After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Y20 and Y23 FPGA pins.
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-===== 10. PC - FPGA Data Transfer (DPTI/DSPI) =====+==== 10. PC - FPGA Data Transfer (DPTI/DSPI) ====
  
 The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design. Both of the interfaces have a software component, a Digilent Adept API and a physical interface between the FPGA and the USB controller. Calling API functions on the PC will either present or request data on the FPGA pins according to the chosen protocol. The functionality is implemented using the on-board dual-port FT2232 USB controller. One port is used exclusively for JTAG, while the other either DPTI or DSPI. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. The Genesys 2 provides two interface types that can be used to transfer user data between a PC and an FPGA design. Both of the interfaces have a software component, a Digilent Adept API and a physical interface between the FPGA and the USB controller. Calling API functions on the PC will either present or request data on the FPGA pins according to the chosen protocol. The functionality is implemented using the on-board dual-port FT2232 USB controller. One port is used exclusively for JTAG, while the other either DPTI or DSPI. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously.
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 {{ :reference:programmable-logic:genesys-2:genesys2_adept.png?550 |Figure 9. USB-FPGA interfaces provided by the USB JTAG port.}} {{ :reference:programmable-logic:genesys-2:genesys2_adept.png?550 |Figure 9. USB-FPGA interfaces provided by the USB JTAG port.}}
  
-==== 10.1. Parallel Transfer Interface (DPTI) ====+=== 10.1. Parallel Transfer Interface (DPTI) ===
  
 DPTI is an 8-bit wide parallel FIFO-style data interface. It offers higher bandwidth than DSPI. In FTDI-terminology, DPTI is equivalent to “FT245-style Asynchronous or Synchronous FIFO Interface”. It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller that is input to the FPGA. In asynchronous mode data transfer is happening on transitions of read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read or free space for data to be written. The FPGA controls data transfer by read, write and output enable signals. DPTI is an 8-bit wide parallel FIFO-style data interface. It offers higher bandwidth than DSPI. In FTDI-terminology, DPTI is equivalent to “FT245-style Asynchronous or Synchronous FIFO Interface”. It is available in both synchronous and asynchronous modes, configurable from the DPTI API. In synchronous mode, data transfer is timed by the clock provided by the USB controller that is input to the FPGA. In asynchronous mode data transfer is happening on transitions of read and write control signals. The USB controller emulates a FIFO memory, providing status signals about the availability of data to be read or free space for data to be written. The FPGA controls data transfer by read, write and output enable signals.
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 For more information, see the [[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf|FT2232H datasheet]]. For more information, see the [[http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf|FT2232H datasheet]].
  
-==== 10.2. Serial Peripheral Interface (DSPI) ====+=== 10.2. Serial Peripheral Interface (DSPI) ===
  
 An industry-standard SPI interface can also be used for transferring data. It uses only four signals for serial full-duplex communication. The USB controller acts as a SPI master, with the FPGA taking the slave role. The USB controller initiates a transaction after API function calls and transfers data in both directions simultaneously.  An industry-standard SPI interface can also be used for transferring data. It uses only four signals for serial full-duplex communication. The USB controller acts as a SPI master, with the FPGA taking the slave role. The USB controller initiates a transaction after API function calls and transfers data in both directions simultaneously. 
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-===== 11. USB HID Host =====+==== 11. USB HID Host ====
  
 The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Genesys 2 with USB HID host capability. After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting on it to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J7 labeled "USB HID”. J7 is a dual-row USB A receptacle, with the top row connected to the Auxiliary Function microcontroller. Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives several signals into the FPGA – two are used to implement a standard PS/2 interface for communication with a mouse or keyboard, and the others are connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB pen drive or microSD card. There is also a second PS/2 interface between the PIC24 and FPGA, however the current firmware does not use it, so those pins may be considered reserved for future use. The Auxiliary Function microcontroller (Microchip PIC24FJ128) provides the Genesys 2 with USB HID host capability. After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting on it to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which is USB HID Host in this case. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J7 labeled "USB HID”. J7 is a dual-row USB A receptacle, with the top row connected to the Auxiliary Function microcontroller. Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives several signals into the FPGA – two are used to implement a standard PS/2 interface for communication with a mouse or keyboard, and the others are connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB pen drive or microSD card. There is also a second PS/2 interface between the PIC24 and FPGA, however the current firmware does not use it, so those pins may be considered reserved for future use.
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 {{ :reference:programmable-logic:genesys-2:genesys2_pic24.png?500 |Figure 10. Genesys 2 PIC24 connections.}} {{ :reference:programmable-logic:genesys-2:genesys2_pic24.png?500 |Figure 10. Genesys 2 PIC24 connections.}}
  
-==== 11.1. HID Controller ====+=== 11.1. HID Controller ===
  
 The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the Genesys 2, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in Figure 11. The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the Genesys 2, the microcontroller emulates a PS/2 device, while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in Figure 11.
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 When a keyboard or mouse is connected to the Genesys 2, a “self-test passed” command (0xAA) is sent to the host. After this, commands may be issued to the device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID command (0xF2). Also, a mouse sends its ID (0x00) right after the “self-test passed” command, which distinguishes it from a keyboard. When a keyboard or mouse is connected to the Genesys 2, a “self-test passed” command (0xAA) is sent to the host. After this, commands may be issued to the device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID command (0xF2). Also, a mouse sends its ID (0x00) right after the “self-test passed” command, which distinguishes it from a keyboard.
  
-==== 11.2. Keyboard ====+=== 11.2. Keyboard ===
  
 PS/2 uses open-collector drivers so the keyboard or an attached host can drive the two-wire bus (if the host will not send data to the keyboard, then the host can use input-only ports). PS/2 uses open-collector drivers so the keyboard or an attached host can drive the two-wire bus (if the host will not send data to the keyboard, then the host can use input-only ports).
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 The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30 kHz) when the data is sent, and data is valid on the falling edge of the clock. The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30 kHz) when the data is sent, and data is valid on the falling edge of the clock.
  
-==== 11.3. Mouse ====+=== 11.3. Mouse ===
  
 Once entered in stream mode and data reporting enabled the mouse outputs a clock and data signal when it is moved: otherwise, these signals remain at logic ‘1.’ Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device, as shown in Figure 10. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.  Once entered in stream mode and data reporting enabled the mouse outputs a clock and data signal when it is moved: otherwise, these signals remain at logic ‘1.’ Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device, as shown in Figure 10. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz. 
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-===== 12. User USB 2.0 =====+==== 12. User USB 2.0 ====
  
 When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides physical layer implementation for any USB 2.0 user-application. It connect to a USB A (J7-bottom row) and a USB AB micro (J6) receptacle in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors. Use only one of the connectors at a time, the one fitting the desired USB role.  When the fixed USB roles of the Genesys2 are not enough, an on-board USB 2.0 transceiver (PHY) provides physical layer implementation for any USB 2.0 user-application. It connect to a USB A (J7-bottom row) and a USB AB micro (J6) receptacle in parallel, enabling device, host, and OTG USB roles without the need for cable adaptors. Use only one of the connectors at a time, the one fitting the desired USB role. 
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-===== 13. Basic I/O =====+==== 13. Basic I/O ====
  
 The Genesys 2 board includes eight slide switches, six push buttons, and eight individual LEDs. The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The five pushbuttons arranged in a plus-sign configuration are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The red pushbutton labeled “CPU RESET,” on the other hand, generates a high output when at rest and a low output when pressed. The CPU RESET button is intended to be used in processor designs to reset the processor, but you can also use it as a general purpose pushbutton. Slide switches generate constant high or low inputs depending on their position. The Genesys 2 board includes eight slide switches, six push buttons, and eight individual LEDs. The pushbuttons and slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The five pushbuttons arranged in a plus-sign configuration are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The red pushbutton labeled “CPU RESET,” on the other hand, generates a high output when at rest and a low output when pressed. The CPU RESET button is intended to be used in processor designs to reset the processor, but you can also use it as a general purpose pushbutton. Slide switches generate constant high or low inputs depending on their position.
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-===== 14. Pmod Connectors =====+==== 14. Pmod Connectors ====
  
 The Pmod connectors are arranged in a 2x6 right-angle, 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two power pins (6 and 12), two ground pins (5 and 11), and eight logic signals, as shown in Figure 20. The VCC and Ground pins of can deliver up to 1A of current per pin. Pin assignments for the Pmod I/O connected to the FPGA are shown in Figure 16. The Pmod connectors are arranged in a 2x6 right-angle, 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two power pins (6 and 12), two ground pins (5 and 11), and eight logic signals, as shown in Figure 20. The VCC and Ground pins of can deliver up to 1A of current per pin. Pin assignments for the Pmod I/O connected to the FPGA are shown in Figure 16.
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 Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See [[/pmod/start|Digilent's Pmod category]] for more information. Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See [[/pmod/start|Digilent's Pmod category]] for more information.
  
-==== 14.1 Dual Analog/Digital Pmod ====+=== 14.1 Dual Analog/Digital Pmod ===
  
 The on-board Pmod expansion connector labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-digital converter inside the Kintex-7 (XADC). Any or all pairs in the connector can be configured either as analog input or digital input-output.  The on-board Pmod expansion connector labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-digital converter inside the Kintex-7 (XADC). Any or all pairs in the connector can be configured either as analog input or digital input-output. 
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 **NOTE:** The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals. **NOTE:** The coupled routing and the anti-alias filters might limit the data speeds when used for digital signals.
  
-The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). This includes access to the temperature sensor and voltage monitors inside the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide” ([[http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf |ug480]]).+The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). This includes access to the temperature sensor and voltage monitors inside the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide” ([[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|ug480]]).
  
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-===== 15. High Pin Count FMC Connector =====+==== 15. High Pin Count FMC Connector ====
  
 The Genesys 2 includes a FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard.  Genesys 2-based designs can now be easily extended with custom or off-the-shelf high-performance modules. The Genesys 2 includes a FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard.  Genesys 2-based designs can now be easily extended with custom or off-the-shelf high-performance modules.
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 Each transceiver lane includes a receive pair and a transmit pair. Lanes DP0-DP3 are wired to quad 115. Lanes DP4-DP7 go to quad 116, along with the two reference clocks GBTCLK0 and GBTCLK1. The last two lanes DP8 and DP9 are connected to quad 117, while the rest of the pins in these three quads are left unused. Each transceiver lane includes a receive pair and a transmit pair. Lanes DP0-DP3 are wired to quad 115. Lanes DP4-DP7 go to quad 116, along with the two reference clocks GBTCLK0 and GBTCLK1. The last two lanes DP8 and DP9 are connected to quad 117, while the rest of the pins in these three quads are left unused.
    
-Since an MGTREFCLK can be routed to both the quad above and below its own, both reference clocks can be used to clock any channel in the three quads. Table 12, Table 13, and Table 14 show how the FMC gigabit signals are mapped to pins and GTX primitives. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide ([[http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf|ug476]]) for more information.+Since an MGTREFCLK can be routed to both the quad above and below its own, both reference clocks can be used to clock any channel in the three quads. Table 12, Table 13, and Table 14 show how the FMC gigabit signals are mapped to pins and GTX primitives. Refer to the 7 Series FPGAs GTX/GTH Transceivers User Guide ([[https://docs.xilinx.com/v/u/en-US/ug476_7Series_Transceivers|ug476]]) for more information.
  
 //Table 12: Quad 115 pinout // //Table 12: Quad 115 pinout //
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-==== 15.1. Routing lengths ====+=== 15.1. Routing lengths ===
 The FMC specification outlines rules on what length mismatch is permissible on different lanes. The signals can be grouped into two categories: Gigabit and User I/O. Differential gigabit lanes permit 1 ps intra-pair mismatch and does not limit inter-pair length mismatch. The reason for the latter is that multi-gigabit protocols have some sort of de-skew mechanism to re-align data between lanes. The FMC specification outlines rules on what length mismatch is permissible on different lanes. The signals can be grouped into two categories: Gigabit and User I/O. Differential gigabit lanes permit 1 ps intra-pair mismatch and does not limit inter-pair length mismatch. The reason for the latter is that multi-gigabit protocols have some sort of de-skew mechanism to re-align data between lanes.
  
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-===== 16. MicroSD Slot =====+==== 16. MicroSD Slot ====
  
 The Genesys 2 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary Function microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller must have access to the SD card via an SPI interface. Once a bit file is downloaded to the FPGA (from any source), the microcontroller powers off the SD slot and relinquishes control of the bus. The FPGA design will find the SD card in an unpowered state. The Genesys 2 provides a microSD slot for both FPGA configuration and user access. The on-board Auxiliary Function microcontroller shares the SD card bus with the FPGA. Before the FPGA is configured the microcontroller must have access to the SD card via an SPI interface. Once a bit file is downloaded to the FPGA (from any source), the microcontroller powers off the SD slot and relinquishes control of the bus. The FPGA design will find the SD card in an unpowered state.
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-===== 17. HDMI =====+==== 17. HDMI ====
  
 The Genesys 2 board contains two buffered HDMI ports: one source port J4 (output), and one sink port J5 (input). Both ports use HDMI type-A receptacles and include HDMI buffer TMDS141. The buffers work by terminating, equalizing, conditioning and forwarding the HDMI stream between the connector and FPGA pins. The Genesys 2 board contains two buffered HDMI ports: one source port J4 (output), and one sink port J5 (input). Both ports use HDMI type-A receptacles and include HDMI buffer TMDS141. The buffers work by terminating, equalizing, conditioning and forwarding the HDMI stream between the connector and FPGA pins.
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 Table 15. HDMI pin description and assignment. Table 15. HDMI pin description and assignment.
  
-==== 17.1. TMDS Signals ====+=== 17.1. TMDS Signals ===
  
 HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS). To make proper use of either of the HDMI ports a standard-compliant transmitter or receiver needs to be implemented in the FPGA. The implementation details are outside the scope of this manual. HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS). To make proper use of either of the HDMI ports a standard-compliant transmitter or receiver needs to be implemented in the FPGA. The implementation details are outside the scope of this manual.
  
-==== 17.2. Auxiliary Signals ====+=== 17.2. Auxiliary Signals ===
  
 Presence of a sink on the cable is announced on the hot-plug detect (HPD) pin. Whenever a sink is ready and wishes to announce its presence, it connects the HPD pin to the 5V0 supply pin. On the Genesys 2 this is achieved by pulling HDMI_RX_HPA high. This signal defaults low. The source reads the HPD pin through an inverting level-translator, so HDMI_TX_HPD reads low when a sink is present. Presence of a sink on the cable is announced on the hot-plug detect (HPD) pin. Whenever a sink is ready and wishes to announce its presence, it connects the HPD pin to the 5V0 supply pin. On the Genesys 2 this is achieved by pulling HDMI_RX_HPA high. This signal defaults low. The source reads the HPD pin through an inverting level-translator, so HDMI_TX_HPD reads low when a sink is present.
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-===== 18. DisplayPort =====+==== 18. DisplayPort ====
  
 DisplayPort is a relatively new industry standard for digital display technology. Its advantages over existing technologies are: higher bandwidth for greater resolutions and color depths, bi-directional auxiliary channel, variable interface width, and flexible power topologies among others. DisplayPort is a relatively new industry standard for digital display technology. Its advantages over existing technologies are: higher bandwidth for greater resolutions and color depths, bi-directional auxiliary channel, variable interface width, and flexible power topologies among others.
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-===== 19. OLED =====+==== 19. OLED ====
  
 A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Genesys 2. It is a white monochrome, 128 x 32, 0.91” organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards the FPGA is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up sequencing. The signals are summarized in Table 17. A Univision Technology Inc. UG-2832HSWEG04 is loaded on the Genesys 2. It is a white monochrome, 128 x 32, 0.91” organic LED display matrix bundled with a Solomon Systech SSD1306 display controller. The display data interface towards the FPGA is a 4-wire serial peripheral interface (SPI). The 4 wires in controller-terminology are CS#, D/C#, SDIN, and SCLK, but CS# is hard-wired to ground. This adds to the reset and two power control signals for proper start-up sequencing. The signals are summarized in Table 17.
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-===== 20. Audio Codec =====+==== 20. Audio Codec ====
  
 The Genesys 2 board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC11) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J11-green), headphone-out (J10-black), line-in (J13-blue), and microphone-in (J12-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono. The Genesys 2 board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC11) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J11-green), headphone-out (J10-black), line-in (J13-blue), and microphone-in (J12-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.