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programmable-logic:eclypse-z7:demos:ddr-streaming [2022/08/15 21:36] – created Arthur Brownprogrammable-logic:eclypse-z7:demos:ddr-streaming [2024/02/27 01:30] (current) – Release 2021.1.2 Arthur Brown
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 +====== Using DDR Buffers with the Eclypse Z7 ======
 +
 +<WRAP round todo>
 +=== Under Construction! ===
 +</WRAP>
 +
 +===== Description =====
 +
 +This demo includes several baremetal software projects that demonstrate the use of DDR buffers in the Eclypse Z7.
 +
 +Xilinx AXI DMA cores in Scatter-Gather mode are used for each input or output data stream in order to allow the processor to enqueue blocks of data as it sees fit, allowing data to be continuously streamed into a slower clock domain. This technique greatly expands the length of acquisitions achievable by the Eclypse, allowing the maximum sample rates supported by the Zmods' ADC and DAC parts to be maintained over millions-of-samples-long buffers. Additionally, a simple trigger system is implemented that is capable of halting an acquisition when one of several conditions occurs. For more information, check out the [[Eclypse Platform Manual]].
 +
 +By default, the hardware platform (in the form of a Vivado project) is configured to acquire and generate signals with a sample rate of 40 MS/s and supports the use of one Zmod Scope 1410-105 and one Zmod AWG 1411 in Zmod ports A and B of the Eclypse, respectively. Instructions are presented on how you can customize the hardware platform for your desired sample rate and chosen Zmods.
 +
 +Additionally, a baremetal project using the Digilent Platform Management Utility (dpmutil) software to read calibration coefficients from Zmods' SYZYGY DNA is included.
 +
 +----
 +===== Inventory =====
 +
 +  * Eclypse Z7 with power supply and microUSB cable
 +  * Zmod/s:
 +    * without user modification of hardware, 1x Zmod Scope 1410-105 and/or 1x Zmod AWG 1411
 +    * with user modification of hardware, any combination of Zmod Scope, AWG, and/or Digitizer
 +
 +  * Some signal to acquire and some load to push a signal into
 +    * An Analog Discovery Pro (ADP3450) mixed-signal oscilloscope and waveform generator was used with some SMA cables and SMA-BNC adapters to test the system
 +
 +  * Vivado and Vitis installations compatible with the latest release of this demo (2021.1)
 +    * //See [[programmable-logic:guides:installing-vivado-and-vitis|Installing Vivado, Vitis, and Digilent Board Files]] for installation instructions.//
 +  * Serial Terminal application to receive messages printed by the demo
 +    * //See [[programmable-logic:guides:serial-terminals:start]] for more information.//
 +
 +----
 +===== Download and Usage Instructions =====
 +
 +First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a //release tag//). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged "20/DMA/2020.1" for the Zybo Z7 is only to be used with the -20 variant of the board and Xilinx tools (Vivado and Vitis) version 2020.1.
 +
 +The latest release version for this demo is highlighted in green.
 +
 +|<80% 30% 70%>|
 +^ Release Tag  ^ Release Downloads  ^
 +| 2021.1.2-prerelease  | {{https://github.com/Digilent/Eclypse-Z7/releases/download/ddr-streaming/2021.1.2-prerelease/Eclypse-Z7-DDR-Streaming-hw.xpr.zip}} \\ {{https://github.com/Digilent/Eclypse-Z7/releases/download/ddr-streaming/2021.1.2-prerelease/Eclypse-Z7-DDR-Streaming-sw.ide.zip}}  |
 +
 +**Note for Advanced Users:** //GitHub sources for this demo can be found in the [[https://github.com/digilent/Eclypse-Z7/tree/ddr-streaming|ddr-streaming]] branch of the Eclypse-Z7 repository. Further documentation on the structure of this repository can be found on this wiki's [[programmable-logic:documents:git]] page.//
 +
 +----
 +
 +--> Using the Latest Release #^
 +<WRAP group>
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_no_build&noheader}}
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_workaround_before_programming&noheader}}
 +
 +--> Build a Vitis Application #
 +<WRAP group>
 +{{page>programmable-logic:guides:vitis-build-software&noheader}}
 +</WRAP>
 +<--
 +
 +--> Set up the Eclypse Z7 #
 +<WRAP group>
 +<WRAP group> <WRAP column half>
 +Connect your Zmods to the Eclypse.
 +
 +Plug the Eclypse into the computer via the microUSB programming cable and connect the power supply. Make sure the JP5 programming mode jumper is set to JTAG. Power on the board.
 +</WRAP> <WRAP column half>
 +FIXME
 +</WRAP> </WRAP>
 +
 +
 +<WRAP group> <WRAP column half>
 +Connect a signal source and/or 
 +Describe ADP+Eclypse test setup
 +</WRAP> <WRAP column half>
 +</WRAP> </WRAP>
 +
 +<WRAP group> <WRAP column half>
 +Three applications projects are provided with the workspace in this demo:
 +  * 'calibration_reader' enumerates the Zmods connected to the Eclypse and reads their calibration data from Syzygy DNA, and prints it to a connected serial terminal.
 +  * 's2mm_cyclic_transfer_test' performs a single triggered acquisition, acquiring a 40.96 us buffer of samples at 100 MS/s. A manual trigger is applied after the demo has been running for 1 second, and a rising level trigger is applied when Scope channel 1 rises past 0 V. Data is dumped to the serial terminal.
 +  * 'mm2s_single_transfer_test' produces a 67 MS buffer filled with ramp waveforms on both channels and plays them out over the AWG outputs until it is halted when any character is received from a connected serial terminal.
 +
 +Note: All applications in this workspace use a baud rate of 115200 for their serial interfaces.
 +</WRAP> <WRAP column half>
 +</WRAP> </WRAP>
 +</WRAP>
 +----
 +<--
 +
 +{{page>programmable-logic:guides:using-github-releases#baremetal_release_programming&noheader}}
 +
 +At this point, the demo is now running on your board. Refer to the [[#description|Description]] section of this document for more information on what it does.
 +----
 +Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.
 +----
 +{{page>programmable-logic:guides:using-github-releases#baremetal_update_specification&noheader}}
 +</WRAP>
 +<--
 +
 +----
 +
 +===== Additional Resources =====
 +
 +All materials related to the use of the Eclypse Z7 can be found in its Resource Center.
 +
 +[[Eclypse Platform Manual]]
 +
 +For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see [[/programmable-logic/guides/getting-started-with-ipi|Getting Started with Vivado and Vitis for Baremetal Software Projects]]. Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.
 +
 +For technical support, please visit the FPGA section of the [[https://forum.digilent.com/forum/4-fpga/|Digilent Forum]].