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programmable-logic:arty-z7:reference-manual [2021/05/14 23:06] – ↷ Links adapted because of a move operation Arthur Brownprogrammable-logic:arty-z7:reference-manual [2023/06/22 21:12] (current) – Arthur Brown
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 ---- ----
  
-====== Features ======+===== Features =====
  
   * **ZYNQ Processor**   * **ZYNQ Processor**
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     * Programmable logic equivalent to Artix-7 FPGA     * Programmable logic equivalent to Artix-7 FPGA
   * **Memory**   * **Memory**
-    * 512MB DDR3 with 16-bit bus @ 1050Mbps+    * 512MB DDR3 with 16-bit bus @ 525MHz (1050MT/s)
     * 16MB Quad-SPI Flash with factory programmed 48-bit globally unique EUI-48/64™ compatible identifier     * 16MB Quad-SPI Flash with factory programmed 48-bit globally unique EUI-48/64™ compatible identifier
     * microSD slot     * microSD slot
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-====== Purchasing Options ======+===== Purchasing Options =====
  
 The Arty Z7 can be purchased with either a Zynq-7010 or Zynq-7020 loaded. These two Arty Z7 product variants are referred to as the Arty Z7-10 and Arty Z7-20, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Arty Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name. The Arty Z7 can be purchased with either a Zynq-7010 or Zynq-7020 loaded. These two Arty Z7 product variants are referred to as the Arty Z7-10 and Arty Z7-20, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Arty Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
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 On the Arty Z7-10, the inner row of the digital shield (IO26-IO41) and IOA (also referred to as IO42) are not connected to the FPGA, and A0-A5 can only be used as analog inputs. This will not affect the functionality of most existing Arduino shields, because most do not use this inner row of digital signals. On the Arty Z7-10, the inner row of the digital shield (IO26-IO41) and IOA (also referred to as IO42) are not connected to the FPGA, and A0-A5 can only be used as analog inputs. This will not affect the functionality of most existing Arduino shields, because most do not use this inner row of digital signals.
  
-The board can be purchased stand-alone or with a voucher to unlock the Xilinx SDSoC toolset. The SDSoC voucher unlocks a 1 year license and can only be used with the Arty Z7. After the license expires, any version of SDSoC that was released during this 1 year period can continue to be used indefinitely. For more information on purchasing, see the [[http://store.digilentinc.com/arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/|Arty Z7 Product Page]]. At the time of purchase, it is also possible to add-on a microSD card, 12V 3A power supply, and micro USB cable as needed. +The board can be purchased stand-alone or with a voucher to unlock the Xilinx SDSoC toolset. The SDSoC voucher unlocks a 1 year license and can only be used with the Arty Z7. After the license expires, any version of SDSoC that was released during this 1 year period can continue to be used indefinitely. For more information on purchasing, see the [[https://digilent.com/shop/arty-z7-zynq-7000-soc-development-board/|Arty Z7 Product Page]]. At the time of purchase, it is also possible to add-on a microSD card, 12V 3A power supply, and micro USB cable as needed. 
  
 Note that due to the smaller FPGA in the Zynq-7010, it is not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the Arty Z7-20 if they are interested in these types of applications. Note that due to the smaller FPGA in the Zynq-7010, it is not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the Arty Z7-20 if they are interested in these types of applications.
  
 ---- ----
-====== Differences from PYNQ-Z1 ======+===== Differences from PYNQ-Z1 =====
 Arty Z7-20 shares the exact same SoC with the PYNQ-Z1. Feature-wise, Arty Z7-20 is missing the microphone input, but adds a Power-on Reset button. Software written for PYNQ-Z1 should run unchanged with the exception of microphone input, whose FPGA pin is left unconnected. Arty Z7-20 shares the exact same SoC with the PYNQ-Z1. Feature-wise, Arty Z7-20 is missing the microphone input, but adds a Power-on Reset button. Software written for PYNQ-Z1 should run unchanged with the exception of microphone input, whose FPGA pin is left unconnected.
  
-====== Software Support ======+===== Software Support =====
  
 The Arty Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Arty Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.  The Arty Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Arty Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. 
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 The Arty Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a Video capable platform with Linux support in time for the SDSoC 2017.1 release. Note that due to the smaller FPGA in the Arty Z7-10, only very basic video processing demos are included with that platform. Digilent recommends the Arty Z7-20 for those interested in video processing. The Arty Z7 can also be used in Xilinx's SDSoC environment, which allows you to design FPGA accelerated programs and video pipelines with ease in an entirely C/C++ environment. For more information on SDSoC, see the [[https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html|Xilinx SDSoC Site]]. Digilent will be releasing a Video capable platform with Linux support in time for the SDSoC 2017.1 release. Note that due to the smaller FPGA in the Arty Z7-10, only very basic video processing demos are included with that platform. Digilent recommends the Arty Z7-20 for those interested in video processing.
  
-Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Arty Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilentinc.com|Digilent Forum]].+Those familiar with the older Xilinx ISE/EDK toolsets from before Vivado was released can also choose to use the Arty Z7 in that toolset. Digilent does not have many materials to support this, but you can always ask for help on the [[https://forum.digilent.com|Digilent Forum]].
  
 ---- ----
  
  
-====== 1 Power Supplies ======+===== 1 Power Supplies =====
  
 The Arty Z7 can be powered from the Digilent USB-JTAG-UART port (J14) or from some other type of power source such as a battery or external power supply. Jumper JP5 (near the power switch) determines which power source is used. The Arty Z7 can be powered from the Digilent USB-JTAG-UART port (J14) or from some other type of power source such as a battery or external power supply. Jumper JP5 (near the power switch) determines which power source is used.
  
-A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This should provide enough power for lower complexity designs. More demanding applications, including any that drive multiple peripheral boards or other USB devices, might require more power than the USB port can provide. In this case, power consumption will increase until it’s limited by the USB host. This limit varies a lot between manufacturers of host computers and depends on many factors. When in current limit, once the voltage rails dip below their nominal value, the Zynq is reset by the Power-on Reset signal and power consumption returns to its idle value. Also, some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply or battery can be used.+A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This should provide enough power for lower complexity designs. More demanding applications, including any that drive multiple peripheral boards or other USB devices, might require more power than the USB port can provide. In this case, power consumption will increase until it is limited by the USB host. This limit varies a lot between manufacturers of host computers and depends on many factors. When in current limit, once the voltage rails dip below their nominal value, the Zynq is reset by the Power-on Reset signal and power consumption returns to its idle value. Also, some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply or battery can be used.
  
 An external power supply (e.g. wall wart) can be used by plugging it into the power jack (J18) and setting jumper JP5 to “REG”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 7VDC to 15VDC. Suitable supplies can be purchased from the Digilent website or through catalog vendors like DigiKey. Power supply voltages above 15VDC might cause permanent damage. A suitable external power supply is included with the Arty Z7 accessory kit. An external power supply (e.g. wall wart) can be used by plugging it into the power jack (J18) and setting jumper JP5 to “REG”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 7VDC to 15VDC. Suitable supplies can be purchased from the Digilent website or through catalog vendors like DigiKey. Power supply voltages above 15VDC might cause permanent damage. A suitable external power supply is included with the Arty Z7 accessory kit.
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 The on-board Texas Instruments TPS65400 PMU creates the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input. Table 1.1 provides additional information (typical currents depend strongly on Zynq configuration and the values provided are typical of medium size/speed designs). The on-board Texas Instruments TPS65400 PMU creates the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the main power input. Table 1.1 provides additional information (typical currents depend strongly on Zynq configuration and the values provided are typical of medium size/speed designs).
  
-The Arty Z7 does not have a power switch, so when a power source is connected and selected with JP5 it will always be powered on. To reset the Zynq without disconnecting and reconnecting the power supply, the red SRST button can be used. The power indicator LED (LD13) is on when all the supply rails reach their nominal voltage.+The Arty Z7 does not have a power switch, so when a power source is connected and selected with JP5 it will always be powered on. To reset the Zynq without disconnecting and reconnecting the power supply, the red SRST button can be used. The power indicator LED (LD13) is on when all the supply rails reach their nominal voltage. A proper power cycle requires the selected power source (USB, external power supply or battery) to be disconnected from the Arty Z7 and kept disconnected for at least 1 second.
  
 | **Supply**  | **Circuits**                                                 | **Current (max/typical)**  | | **Supply**  | **Circuits**                                                 | **Current (max/typical)**  |
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 ---- ----
  
-====== 2 Zynq APSoC Architecture ======+ 
 +---- 
 +==== Note: Sequencing Changes from Revision D.0 ==== 
 + 
 +The power supply circuitry is slightly different depending on the revision of your board. Changes were introduced in Revision D.0 to conform to sequencing requirements imposed by changing the PHY part used from the RTL8211E to the RTL28211F Ethernet PHY. Of particular note is the addition of a load switch separating all I/O circuitry connected to Zynq bank 501 (Ethernet, USB, UART, SD) from the main 1.8 V board supply. These changes mean that board power-on now takes more time. The dropdown below contains the power circuit overview diagram for revisions prior to D.0: 
 + 
 +--> Power Circuit Overview - Revision < D.0 # 
 +{{:programmable-logic:arty-z7:powercircuit.png?600|}} 
 +<-- 
 + 
 +---- 
 + 
 +===== 2 Zynq APSoC Architecture =====
  
  The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic (PL). Figure 2.1 shows an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7020 or Zynq-7010 devices.   The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic (PL). Figure 2.1 shows an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7020 or Zynq-7010 devices. 
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference Manual]]. 
  
 Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals.  Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. 
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 ---- ----
  
-====== 3 Zynq Configuration ======+===== 3 Zynq Configuration =====
  
 Unlike Xilinx FPGA devices, APSoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application.  Unlike Xilinx FPGA devices, APSoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application. 
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 **Stage 2**  **Stage 2** 
  
-The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The last stage is the execution of the user application that was loaded by the FSBL. This can be any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used to boot an operating system like Linux. For a more thorough explanation of the boot process, refer to Chapter 6 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
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 ---- ----
  
-====== 4 Quad SPI Flash ======+===== 4 Quad SPI Flash =====
  
 The Arty Z7 features a Quad SPI serial NOR flash. This Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem.  The Arty Z7 features a Quad SPI serial NOR flash. This Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem. 
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   * 16 MB    * 16 MB 
   * x1, x2, and x4 support    * x1, x2, and x4 support 
-  * Bus speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz. In Quad SPI mode, this translates to 400Mbs +  * Bus speeds up to 104 MHz, supporting Zynq configuration rates @ 100 MHz. In Quad SPI mode, this translates to 400 Mb/s 
   * Powered from 3.3V    * Powered from 3.3V 
  
-The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]] for more on this). +The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]] for more on this). 
  
-In manufacturing, parts sometimes need to be replaced when the product goes end-of-life. The Quad SPI Flash memory on any particular Arty Z7 may be one of the drop-in replacements found in the Table 4.1 below. To determine which part is used by a particular board, look at the part number printed on IC19 on the bottom of the Arty Z7 (See Figure 4.1).+In manufacturing, parts sometimes need to be replaced when the product goes end-of-life. The Quad SPI Flash memory on any particular Arty Z7 may be one of several found in Table 4.1 below. To determine which part is used by a particular board, check your boards revision number and look at the part number printed on the flash IC on the bottom of the Arty Z7 (See Figure 4.1).
  
 {{:reference:programmable-logic:arty-z7:arty-z7-flash-callout-600.png?nolink&400|}} {{:reference:programmable-logic:arty-z7:arty-z7-flash-callout-600.png?nolink&400|}}
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 //Figure 4.1. Arty Z7 Flash IC Location// //Figure 4.1. Arty Z7 Flash IC Location//
  
-^ Manufacturer  ^ Part Number  ^ +^ Manufacturer  ^ Part Number            | PCB Board Revision  | 
-| Spansion  | S25FL128SAGMFI00  | +| Winbond       | W25Q128JV[SP]xM        | ≥ D.0               | 
-| Micron  | MT25QL128ABA8ESF-0SIT  | +| Micron        | MT25QL128ABA8ESF-0SIT  | < D.0               | 
-| Micron  | MT25QL128ABA8ESF-0AAT  | +| Micron        | MT25QL128ABA8ESF-0AAT  | < D.0               | 
-| Micron  | N25Q128A13ESF40E  |+| Micron        | N25Q128A13ESF40E       | < D.0               | 
 +| Spansion      | S25FL128SAGMFI00       | < D.0               |
  
 //Table 4.1. Arty Z7 Flash IC Drop-in Replacements// //Table 4.1. Arty Z7 Flash IC Drop-in Replacements//
 +
 +The part numbers are highly compatible, however, the W25Q128JV is not functionally equivalent to the previously-loaded parts and might require changes to customer applications (embedded software) depending on the board support package in use (OS, drivers, and libraries). Spansion and Micron parts used on revisions of the board < D.0 are functionally equivalent to each other from the perspective of user software. It might be possible to implement any changes that might be needed in such a way as to keep compatibility with all load options. A non-exhaustive list of the differences between the W25Q128JV and the S25FL128S:
 +
 +  * Manufacturer & Device ID: “EFh 70h 18h” vs. “01h 20h 18h”
 +  * 3x256-B Security Registers vs. 32x32-B OTP Array
 +  * Security Register Read command 48h vs. OTP Read command 4Bh
 +  * Memory organization: 256 64KB or 4096 4KB uniform erase sectors vs. 32 4-KB bottom and 256 64-KB hybrid erase sectors
 +  * For revisions prior to D.0, the OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the OTP region. The W25Q128JV's Security Registers do not have this random number.
 +  * Maximum clock frequency for QPP, 4QPP commands: 133 MHz vs. 80MHz.
 +
 +Embedded software work-arounds depending on the board support package:
 +
 +  * Stand-alone environments should be modified if special non-standard commands are in use. For example, OTP read/write features should account for opcode and address changes. Standard flash array read and write commands, single or quad are compatible between the two.
 +  * The MAC address for the Gigabit Ethernet port needs to be read out using the Read Security Registers (48h) command and the address range [001000h;001005h]. The byte order is the same as before, ie. the first byte in transmission byte order is at the lowest address.
 +  * Xilinx tools such as Vitis and Vivado support the W25Q128JV once the correct part number is chosen when targeting the Flash memory. Choose the “w25q128fv-qspi-x4-single” option which is an alias for the “w25q128jv-qspi-x4-single”. Support for w25q128jv is available in version 2018.3 and above.
 +  * U-boot and Linux kernel built using the “jedec,spi-nor” compatibility string for the flash node needs no changes, as the part is identified during probe. If the old way of specifying a fixed part is used, it is recommended that the compatibility string is replaced with “jedec,spi-nor”.
 +
 +**Note:** //Refer to the manufacturers' datasheets[([[https://www.infineon.com/dgdl/Infineon-S25FL128S_S25FL256S_128_Mb_(16_MB)_256_Mb_(32_MB)_3.0V_SPI_Flash_Memory-DataSheet-v18_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ecfb6a64a17|S25FL128S Datasheet]])][([[https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf|W25Q128JV Datasheet]])] [([[https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf|MT25QL128ABA8ESF-0SIT]])] [([[https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qlhs_l_128_aba_0.pdf|MT25QL128ABA8ESF-0AAT]])] [([[https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf?rev=9d6336dba62c476fbec1db38ee83553a| N25Q128A13ESF40E]])] and Zynq Technical Reference Manual[([[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Xilinx Zynq Technical Reference Manual (UG585)]])] for more information.//
 +
 +~~REFNOTES~~
  
 ---- ----
  
-====== 5 DDR Memory ======+---- 
 + 
 +===== 5 DDR Memory =====
  
 The Arty Z7 includes an IS43TR16256A-125KBL DDR3 memory components creating a single rank, 16-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.  The Arty Z7 includes an IS43TR16256A-125KBL DDR3 memory components creating a single rank, 16-bit wide interface and a total of 512MiB of capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation. 
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 Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Arty Z7 memory interface PCB design.  Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Arty Z7 memory interface PCB design. 
  
-For more details on memory controller operation, refer to the Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more details on memory controller operation, refer to the Xilinx [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ¹Maximum actual clock frequency is 525 MHz on the Arty Z7 due to PLL limitation. ¹Maximum actual clock frequency is 525 MHz on the Arty Z7 due to PLL limitation.
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 ---- ----
  
-====== 6 USB UART Bridge (Serial Port) ======+===== 6 USB UART Bridge (Serial Port) =====
  
 The Arty Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J14) that lets you use PC applications to communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller. The Arty Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J14) that lets you use PC applications to communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.
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 ---- ----
  
-====== 7 microSD Slot ======+===== 7 microSD Slot =====
  
-The Arty Z7 provides a microSD slot (J9) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 7.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.+The Arty Z7 provides a microSD slot (J9) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-47], including Card Detect. On the PS side peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 7.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]], SDIO host mode is the only mode supported.
  
 | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  | | **Signal Name**  | **Description**  | **Zynq Pin**  | **SD Slot Pin**  |
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 Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz. A Class 4 card or better is recommended.  Both low speed and high speed cards are supported, the maximum clock frequency being 50 MHz. A Class 4 card or better is recommended. 
  
-Refer to section 3.1 for information on how to boot from an SD card. For more information, consult the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+Refer to section 3.1 for information on how to boot from an SD card. For more information, consult the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
 ---- ----
  
-====== 8 USB Host ======+===== 8 USB Host =====
  
-The Arty Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.  +The Arty Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Texas Instruments TUSB1210 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.
  
-The Arty Z7 is technically an “embedded host”, because it does not provide the required 150 µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Arty Z7 so that it complies with the general purpose USB host requirements by loading C41 with a 150 µF capacitor. Only those experienced at soldering small components on PCBs should attempt this rework. Many USB peripheral devices will work just fine without loading C41. Whether the Arty Z7 is configured as an embedded host or a general purpose host, it can provide 500 mA on the 5V VBUS line. Note that loading C41 may cause the Arty Z7 to reset when booting embedded Linux while powered from the USB port, regardless of if any USB device is connected to the host port. This is caused by the in-rush current that C41 causes when the USB host controller is enabled and the VBUS power switch (IC9) is turned on.+The Arty Z7 is technically a “general purpose host”, because it provides the required 150 µF of capacitance on VBUS. The Arty Z7 can provide 500 mA on the 5V VBUS line.
  
 Note that if your design uses the USB Host port (embedded or general purpose), then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power (such as the one included in the Arty Z7 accessory kit).  Note that if your design uses the USB Host port (embedded or general purpose), then the Arty Z7 should be powered via a battery or wall adapter capable of providing more power (such as the one included in the Arty Z7 accessory kit). 
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 ---- ----
  
-====== 9 Ethernet PHY ======+===== 9 Ethernet PHY =====
  
-The Arty Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. +The Arty Z7 uses a Realtek PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. 
  
-{{ reference:programmable-logic:arty-z7:arty-z7-eth.png?500 |}}+One of several Realtek PHY parts may be loaded on your board, depending on the revision of the board. To find out which part is loaded, check the PCB revision on the underside of the PCB. These devices are not functionally equivalent and may require changes to user applications,​ depending on the board support package (OS, drivers, and libraries) used. The table below lists the possible load options, and a non-exhaustive list of the differences between these two PHY devices is presented at the end of this section.  
 + 
 +//Table 9.1: Ethernet PHY part loaded//  
 +^ P/N       ^ PCB Revision  ^ 
 +| RTL8211E  | < D.0         | 
 +| RTL8211F  | ≥ D.0         |
  
 +--> Ethernet PHY - Revision ≥ D.0 ^#
 +{{ :programmable-logic:arty-z7:arty-z7-d0-eth.png?500 |}}
 //Figure 9.1. Ethernet PHY signals// //Figure 9.1. Ethernet PHY signals//
 +<---
 +
 +--> Ethernet PHY - Revision < D.0 # 
 +{{ reference:programmable-logic:arty-z7:arty-z7-eth.png?500 |}}
 +//Figure 9.1. Ethernet PHY signals//
 +
 +<---
  
 After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured. After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the Zynq not configured.
  
-Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD9) and valid link state (LD8). Table 9.1 shows the default behavior.+Three status indicator LEDs, labeled "10", "100", and "1G" near the RJ-45 connector indicate both status and link state of the three connection speeds. Table 10.1 shows the default behavior. 
 + 
 +|  **Designator**  |  **State**  |  **Description**           | 
 +|  10              | Steady on   | Link Up at 10 Mbps         | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 +|  100             | Steady on   | Link Up at 100 Mbps        | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 +|  1G              | Steady on   | Link Up at 1000 Mbps       | 
 +| :::              | Blinking    | Transmitting or Receiving  | 
 + 
 +//Table 9.2. Ethernet status LEDs// 
 + 
 +Prior to revision D.0, only two status indicator LEDs were used ("LINK" and "ACT"). Check the dropdown below to determine their behavior. 
 + 
 +--> Revision < D.0 LED Behavior #
  
 |  **Function**  |  **Designator**  |  **State**                |  **Description**                            | |  **Function**  |  **Designator**  |  **State**                |  **Description**                            |
-|  LINK          |  LD8             | Steady On                 | Link 10/100/1000                            |+|  LINK          |  LD7             | Steady on                 | Link 10/100/1000                            |
 | :::            | :::              | Blinking 0.4s ON, 2s OFF  | Link, Energy Efficient Ethernet (EEE) mode  | | :::            | :::              | Blinking 0.4s ON, 2s OFF  | Link, Energy Efficient Ethernet (EEE) mode  |
-|  ACT           |  LD9             | Blinking                  | Transmitting or Receiving                   |+|  ACT           |  LD8             | Blinking                  | Transmitting or Receiving                   | 
 +//Table 9.3. Ethernet status LEDs//
  
 +<--
  
-//Table 9.1. Ethernet status LEDs.// 
  
 The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq Presets file, available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]]. The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY is connected. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Arty Z7 Zynq Presets file, available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]].
  
-Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The RTL8211E-VL is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.+Although the default power-up configuration of the PHY might be enough in most applications, the MDIO bus is available for management. The PHY is assigned the 5-bit address 00001 on the MDIO bus. With simple register read and write commands, status information can be read out or configuration changed. The Realtek PHY follows industry-standard register map for basic configuration.
  
-The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The RTL8211E-VL is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer.+The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The PHY is capable of inserting a 2ns delay on both the TXC and RXC so that board traces do not need to be made longer.
  
-The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source.+In revisions < D.0, the PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source.
  
-On an Ethernet network each node needs a unique MAC address. To this end, the one-time-programmable (OTP) region of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/64™ compatible identifier. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. Refer to the Flash memory datasheet that is associated for the chip loaded on the board (see the __[[programmable-logic:arty-z7:reference-manual#quad_spi_flash|Quad SPI Flash]]__ section for more details) for information on how to access the OTP regions. When using Petalinux, this is automatically handled in the U-boot boot-loader, and the Linux system is automatically configured to use this unique MAC address.+On an Ethernet network, each node needs a unique MAC address. The Quad-SPI flash memory is programmed with a 48-bit globally unique EUI-48/64™ compatible identifier during manufacturing. Due to changes in which flash part is loaded on the Arty Z7, accessing the MAC address differs slightly depending on which revision of the board you have. For revisions prior to F.0, the MAC address is contained in the one-time-programmable (OTP) region of the Quad-SPI flash. The OTP address range [0x20;0x25] contains the identifier with the first byte in transmission byte order being at the lowest address. For revisions after and including F.0, the MAC address is contained in the security registers and needs to be read out using the Read Security Registers (48h) command from the address range [001000h;001005h]. The byte order is the same as in older revisions, ie. the first byte in transmission byte order is at the lowest address. Refer to the Flash memory datasheet that is associated with the chip loaded on the board (see the __[[programmable-logic:arty-z7:reference-manual#quad_spi_flash|Quad SPI Flash]]__ section for more details) for information on the commands required to access these memory regions.
  
-For more information on using the Gigabit Ethernet MAC, refer to the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+For more information on using the Gigabit Ethernet MAC, refer to the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
 ---- ----
  
-====== 10 HDMI =======+Differences between the RTL8211E and RTL8211F: 
 + 
 +  * PHYSR1 (PHY Specific Status Register 1) at Page 0xA43, Address 0x1A vs. PHYSR at Address 0x11. Register field layout also differs. Affected functionality includes auto-negotiated speed, duplex and link detection. 
 +  * INSR (Interrupt Status Register) at Page 0xA43, Address 0x1D vs. INSR at Address 0x13. Register field layout also differs. Affected functionality is interrupt detection. 
 +  * INER (Interrupt Enable Register) power-on defaults to only the PHY Register Accessible Interrupt being enabled vs. all interrupt sources enabled. Interrupt sources must now be explicitly enabled, if required. 
 +  * Power-on sequencing requirements changed. The RTL8211F now regulates its own core voltage, as its internal regulator cannot be turned off. The 1.8V I/O voltage sequencing requirements forced all I/O circuitry in bank 501 (Ethernet, USB, UART, SD) to be separated from the main 1.8V board supply by a load switch. This I/O supply is now the last in the sequence to power-on. The board power-on reset circuitry required to be changed as well. Power-on now takes more time. 
 +  * Power-on core logic ready time 100 ms vs. 20 ms. The RTL8211F reserves a 100 ms window after power-on that is not being used for now. The only register access allowed in this window is Page 0xa46, Reg. 20, bit[1]=1 (PHY Special Config Done), to skip this window and enter normal operating state. Otherwise, the PHY will do it automatically when the wait period ends. Entering normal operating state is signaled by the ETH_INT_B interrupt. This behavior affects only very short boot time applications, which have been explicitly optimized for this purpose. Such applications must make sure they monitor the PHY interrupt and do not access any registers other than the one stated above before the Special Config Done even arrives. The typical boot time of a small non-optimized stand-alone application from the QSPI flash is 86 ms from the de-assertion the PS_POR_B signal. The PS_POR_B delay was increased and the PHY is now taken out of reset ahead of the Zynq. Therefore, without specific boot time optimizations, the RTL8211F is guaranteed to be ready by the time the software needs it. 
 +  * Three PHY status LEDs vs. two. The Link and Activity LEDs have been replaced by one LED for each link speed that integrate link and activity. These are now labeled “10”, “100”, and “1G”. 
 + 
 +---- 
 + 
 +Suggested embedded software work-arounds depending on the board support package: 
 + 
 +  * Stand-alone environments are expected to be using Xilinx’s lwip library with built-in PHY support for the RTL8211E. This will need to be replaced by a modified library that adds support for the RTL8211F. The patched library is published on Digilent’s Github page: [[https://github.com/Digilent/embeddedsw/tree/realtek-21.1|Patched Library]]. It is expected to be upstreamed to Xilinx in a future Vitis version. \\ If the ETH_INT_B interrupt is used in the application, the necessary interrupt sources must now be enabled explicitly. \\ If the application optimizes boot time, the PHY needs to be initialized by writing Page 0xa46, Reg. 20, bit[1]=1 (PHY Special Config Done). 
 +  * U-boot and Linux kernel built using Petalinux 2016.1 or later support RTL8211F with no changes necessary. 
 + 
 +---- 
 + 
 + 
 +===== 10 HDMI =====
  
 The Arty Z7 contains two unbuffered HDMI ports: one source port J11 (output), and one sink port J10 (input). Both ports use HDMI type-A receptacles with the data and clock signals terminated and connected directly to the Zynq PL. The Arty Z7 contains two unbuffered HDMI ports: one source port J11 (output), and one sink port J10 (input). Both ports use HDMI type-A receptacles with the data and clock signals terminated and connected directly to the Zynq PL.
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 The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. All non-power signals are wired to the Zynq PL with the exception of RES. The 19-pin HDMI connectors include three differential data channels, one differential clock channel five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. All non-power signals are wired to the Zynq PL with the exception of RES.
 +
 +Note that if you use the HDMI source port, in order to ensure the minimum level of the 5V signal is at least 4.8V as required by the HDMI specification, the Arty Z7 should be powered via a wall adapter (such as the one included in the Arty Z7 accessory kit); thus, the 5V level will be established by the IC24 on-board regulator. Otherwise, USB power can provide a voltage as low as 4.75V, which would be too low for the HDMI source port 5V signal.
  
 ^ Pin/Signal          ^ J11 (source)                                                      |^ <color #ed1c24>J10 (sink)</color>                                                                               || ^ Pin/Signal          ^ J11 (source)                                                      |^ <color #ed1c24>J10 (sink)</color>                                                                               ||
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 ---- ----
  
-====== 11 Clock Sources ======+===== 11 Clock Sources =====
  
 The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Arty Z7 Zynq Presets file available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock. The Arty Z7 provides a 50 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 50 MHz input allows the processor to operate at a maximum frequency of 650 MHz and the DDR3 memory controller to operate at a maximum of 525 MHz (1050 Mbps). The Arty Z7 Zynq Presets file available on the [[programmable-logic:arty-z7:start|Arty Z7 Resource Center]] can be imported into the Zynq Processing System IP core in a Vivado project to properly configure the Zynq to work with the 50 MHz input clock.
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 ---- ----
  
-====== 12 Basic I/O ======+===== 12 Basic I/O =====
  
 The Arty Z7 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs as shown in Figure 12.1. The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide switch was inadvertently defined as an output). The four push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position. The Arty Z7 board includes two tri-color LEDs, 2 switches, 4 push buttons, and 4 individual LEDs as shown in Figure 12.1. The push buttons and slide switches are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button or slide switch was inadvertently defined as an output). The four push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches generate constant high or low inputs depending on their position.
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 ---- ----
  
-======13 Mono Audio Output======+=====13 Mono Audio Output=====
  
 The on-board audio jack (J13) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono audio output. The circuit of the low-pass filter is shown in Figure 14.1. The input of the filter (AUD_PWM) is connected to the Zynq PL pin R18. A digital input will typically be a pulse-width modulated (PWM) or pulse density modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width modulated digital signal into an analog voltage on the audio jack output. The on-board audio jack (J13) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono audio output. The circuit of the low-pass filter is shown in Figure 14.1. The input of the filter (AUD_PWM) is connected to the Zynq PL pin R18. A digital input will typically be a pulse-width modulated (PWM) or pulse density modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width modulated digital signal into an analog voltage on the audio jack output.
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 ---- ----
  
-====== 14 Reset Sources ======+===== 14 Reset Sources =====
  
-==== 14.1 Power-on Reset ====+==== 14.1 Power-on Reset Signals ====
  
 The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Arty Z7 drives this signal from the PGOOD signal of the TPS65400 power regulator in order to hold the system in reset until all power supplies are valid.  The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Arty Z7 drives this signal from the PGOOD signal of the TPS65400 power regulator in order to hold the system in reset until all power supplies are valid. 
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 ---- ----
  
-====== 15 Pmod Ports ======+===== 15 Pmod Ports =====
  
 Pmod ports are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 15.1. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail current limits listed in the "Power Supplies" section).  Pmod ports are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 15.1. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail current limits listed in the "Power Supplies" section). 
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 ---- ----
  
-====== 16 Arduino/chipKIT Shield Connector ======+===== 16 Arduino/chipKIT Shield Connector =====
 The Arty Z7 can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Arty Z7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 49 pins connected to the Zynq PL for general purpose Digital I/O on the Arty Z7-20 and 26 on the Arty Z7-10. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another six (labeled AN6-11) can be used as differential analog inputs. The Arty Z7 can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Arty Z7 to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 49 pins connected to the Zynq PL for general purpose Digital I/O on the Arty Z7-20 and 26 on the Arty Z7-10. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another six (labeled AN6-11) can be used as differential analog inputs.
  
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 //Table 16.1.1. Shield Digital Voltages.// //Table 16.1.1. Shield Digital Voltages.//
  
-For more information on the electrical characteristics of the pins connected to the Zynq PL, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf|Zynq-7000 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the Zynq PL, please see the [[https://docs.xilinx.com/v/u/en-US/ds187-XC7Z010-XC7Z020-Data-Sheet|Zynq-7000 datasheet]] from Xilinx.
  
 ==== 16.2 Shield Analog I/O ==== ==== 16.2 Shield Analog I/O ====
Line 611: Line 696:
 //Figure 16.2.2. Differential Analog Inputs.// //Figure 16.2.2. Differential Analog Inputs.//
  
-The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].+The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter". It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM|Zynq Technical Reference manual]].
  
  
-====== Hardware errata ======+===== Hardware errata =====
 Although we strive to provide perfect products, we are not infallible. The Arty Z7 is subject to the limitations below. Although we strive to provide perfect products, we are not infallible. The Arty Z7 is subject to the limitations below.
 ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^ ^ Product Name  ^ Variant  ^ Revision  ^ Problem                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ^ Status        ^
-| Arty Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Arty (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Arty (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://www.xilinx.com/support/answers/53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |+| Arty Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >2017.4:\\ [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal, but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Arty (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration, 0 is used as an initial value instead of the negative preset delays. After calibration, if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Arty (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: [[https://support.xilinx.com/s/article/53039]]. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given.  | will not fix  |
  
 {{tag>rm doc arty-z7}} {{tag>rm doc arty-z7}}