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pmod:pmodi2s:reference-manual [2021/10/13 20:57] – external edit 127.0.0.1 | pmod:pmodi2s:reference-manual [2022/09/13 17:55] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey | ||
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+ | ====== Pmod I2S Reference Manual ====== | ||
+ | <WRAP round info 650px> | ||
+ | ===Note=== | ||
+ | The Pmod I2S has been replaced with the [[https:// | ||
+ | </ | ||
+ | |||
+ | The Digilent Pmod I2S (Revision A) is a stereo audio module that accepts all major audio data interface formats and sample rates. | ||
+ | |||
+ | {{Digilent Image Gallery | ||
+ | | image = {{: | ||
+ | | image = {{: | ||
+ | | image = {{: | ||
+ | | image = {{: | ||
+ | }} | ||
+ | |||
+ | == Download This Reference Manual == | ||
+ | * {{: | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ===== Features ===== | ||
+ | * Stereo 24-bit %%D/A%% converter | ||
+ | * Output converted audio signals through standard headphone jack | ||
+ | * Supports all major audio data interface formats | ||
+ | * Accepts 16-24 bits of audio data | ||
+ | * 6-pin Pmod port with %%GPIO%% interface | ||
+ | |||
+ | ---- | ||
+ | =====Functional Description ===== | ||
+ | The %%Pmod I2S%% utilizes a [[https:// | ||
+ | |||
+ | ---- | ||
+ | ===== Interfacing with the Pmod===== | ||
+ | The %%Pmod I2S%% communicates with the host board via the [[pmod: | ||
+ | |||
+ | The fastest clock signal will be the Master Clock (MCLK); as the name implies, this signal will keep everything nicely synchronized. The sample rate (Fs) clock, also known as the Left-Right Clock (LRCK) or the Word Select (WS) clock, indicates when a particular set of data is to be placed on the left or right audio channel for stereo sound. | ||
+ | |||
+ | The final clock is the bit clock, labeled as the Serial Clock (SCK) on the Pmod. This clock can either be provided as a signal from the host board, or can be internally derived by the Pmod itself by providing at least two consecutive frames of the LRCK without providing any SCK signals. The on-board chip will then measure the Master Clock rate and the LRCK rate and determine an appropriate bit clock rate. However, the MCLK/LRCK ratio must meet a set ratio in order to generate an internal SCK, as outlined in the table below from the CS4344 datasheet. | ||
+ | |||
+ | ^ Internal SCK Mode ^ External SCK Mode | | ||
+ | | 16-bit data and SCK = 32*Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 | Up to 24-bit data with data valid on the rising edge of SCK | | ||
+ | | Up to 24-bit data and SCK = 48*Fs if MCLK/LRCK = 768, 384, 192, or 96 |:::| | ||
+ | | Up to 24-bit data and SCK = 72*Fs if MCLK/LRCK = 1152 |:::| | ||
+ | |||
+ | The ratio between the MCLK and the LRCK rates must be an integer ratio so that the internal clock dividers can determine an appropriate bit rate. A table of commonly used sample rates and their corresponding MCLK rates from the CS4344 datasheet is provided below: | ||
+ | |||
+ | ^ LRCK (kHz) ^ MCLK (MHz) | ||
+ | | ::: | ||
+ | | 32 | ||
+ | | 44.1 | ||
+ | | 48 | ||
+ | | 64 | ||
+ | | 88.2 | ||
+ | | 96 | ||
+ | | 128 | 8.1920 | ||
+ | | 176.4 | 11.2896 | ||
+ | | 192 | 12.2880 | ||
+ | ^ Mode | ||
+ | |||
+ | |||
+ | |||
+ | The I²S protocol requires that data is clocked in on the falling edge of the bit clock. The first bit of data (MSB) is not clocked in on the falling edge until a first complete bit clock cycle has passed after the LRCK has changed state. The rising edge of the bit clock clock informs the on board chip that the next bit of data can be read. | ||
+ | |||
+ | The delay of one bit clock cycle before transferring data at each LRCK change also implies that the least significant bit (LSB) of data will be transferred after the LRCK change has occurred. No particular phase relationship must be followed with this on-board chip, although the phase relationship must stay consistent throughout audio session. An example timing diagram of I²S from [[http:// | ||
+ | |||
+ | {{ pmod: | ||
+ | |||
+ | ==== Pinout Description Table ==== | ||
+ | ^ Pin ^ Signal | ||
+ | | 1 | MCLK | Master Clock | | ||
+ | | 2 | LRCK | Left-right Clock | | ||
+ | | 3 | SCK | ||
+ | | 4 | SDIN | Serial Data input | | ||
+ | | 5 | GND | ||
+ | | 6 | VCC | ||
+ | |||
+ | Any external power applied to the %%Pmod I2S%% must be within 3V and 5.25V; however, it is recommended that Pmod is operated at 3.3V. | ||
+ | |||
+ | ---- | ||
+ | ===== Physical Dimensions ===== | ||
+ | The pins on the pin header are spaced 100 mil apart. The PCB is 1 inch long on the sides parallel to the pins on the pin header and 0.8 inches long on the sides perpendicular to the pin header. | ||
+ | |||
+ | ---- | ||
+ | ===== Additional Information ===== | ||
+ | The schematics of the %%Pmod I2S%% are available {{reference: | ||
+ | |||
+ | Example code demonstrating how to get information from the %%Pmod I2S%% can be found [[pmod: | ||
+ | |||
+ | If you have any questions or comments about the %%Pmod I2S%%, feel free to post them under the appropriate section (" |