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Using Digilent Github Demo Projects
Overview
Digilent provides several projects through Github that are designed to demonstrate different uses of our FPGA and Zynq boards. This guide will describe how to download and use these projects.
At the end of this tutorial you will have your demo project running on your board.
Prerequisites
Hardware
- A Supported Digilent 7-Series FPGA or Zynq Board
- USB Cables
Software
- Xilinx Vivado 2016.X
- Vivado 2016.4 is used in this tutorial
- Digilent Board Support Files
- Follow the wiki guide on how to install Board Support Files for Vivado 2015.X
- Projects Supported by this Tutorial
-
Platform Project Name Uses SDK Hardware Handoff Available Wiki Link Github Link Arty Pmod VGA Demo No No Internal Link External Link Zybo DMA Demo Yes Yes Internal Link External Link
Important
For further requirements, please review the project's wiki page.
Tutorial
1. Download the Project ZIP from the Digilent Github
1.3) All of the necessary files are included within each project folder, with relative file paths established, so as long as the files aren't moved around within the folder, you can move and run the project from any location.
2. Open the Project
Select the “SDK Hardware Handoff” option if your project supports Vivado SDK and you want to jump directly in, otherwise select the “Vivado Block Design or HDL Only” option. Review the Supported Projects table above to determine if the Hardware Handoff option is available.
- Vivado Block Design or HDL Only
-
2.2) Open Vivado and find the Tcl Console on the bottom of the window. Enter the letters 'cd' (change directory) followed by the file path you copied earlier.
Important
Select the proj folder from the drop-down menu to make sure that Vivado converts the path's back slashes ' / ' to forward slashes ' \ '. Vivado will not recognize the path otherwise.
2.4) The project will now be open in Vivado and you can navigate through the Design Sources subwindow or select Open Block Design in the project flow manager to the left to see how the project hardware works. (Not all projects will have a block design)
- SDK Hardware Handoff
-
2.1) Find and Launch Vivado SDK.2.6) Make sure that the hw_handoff, application, and application board support package (BSP) project are all checked, then click Finish to pull the projects into SDK.
TIP
Some common issues at this stage can be solved by right clicking the BSP project and selecting Regenerate BSP Sources.
3. Compile, Program, and Run the Project
The options in this step carry through from step 2. If you chose SDK Hardware Handoff before, select that again, otherwise, select the option that applies to the project you are working with. Review the Supported Projects table to help determine what kind of project you are working with.
- HDL Only
-
3.1) Click Generate Bitstream on the left hand menu towards the bottom. In the “Launch Runs” dialog, make sure Launch runs on local host is selected and click OK. In the “No Implementation Results Available” dialog, click Yes to run synthesis and implementation.
Tip
If your computer has multiple cores, you can increase the number of jobs to make this process faster.
3.2) When this process has finished, which may take a while, in the “Bitstream Generation Completed” dialog, select Open Hardware Manager and click OK. Other interesting options here include “Open Implemented Design” which will show how your project logic will be placed on the FPGA. “View Reports” will show a number of different statistics about your project, including how well it meets timing requirements and what resources of your board will be used.
3.3) After the last step, if you don't have the hardware manager opened, select Hardware Manager from the Program and Debug section of the Flow Navigator to the left, just underneath Generate Bitstream.Important
The project may have further setup requirements, such as connecting a serial terminal to your board, visit it's wiki page to make sure.