Using Digilent Github Demo Projects

Digilent provides several projects through Github that are designed to demonstrate different uses of our FPGA and Zynq boards. This guide will describe how to download and use these projects.

At the end of this tutorial you will have your demo project running on your board.

• A Supported Digilent 7-Series FPGA or Zynq Board
• USB Cables

• Xilinx Vivado 2016.X
  • Vivado 2016.4 is used in this tutorial
• Digilent Board Support Files
  • Follow the wiki guide on how to install Board Support Files for Vivado 2015.X

Projects Supported by this Tutorial

Platform	Project Name	Uses SDK	Hardware Handoff Available	Wiki Link	Github Link
Arty	Pmod VGA Demo	No	No	Internal Link	External Link
Zybo	DMA Demo	Yes	Yes	link	link

1.1) From the demo repository landing page, select the release link.

1.2) If the repository has multiple releases, select Latest Release, then click on the project ZIP file included in the Downloads section of the release to download it.

Important

Make sure that you download the project-2016.4-x.zip, not the source code archive.

1.3) All of the necessary files are included within each project folder, with relative file paths established, so as long as the files aren't moved around within the folder, you can move and run the project from any location.

Select the “SDK Hardware Handoff” option if your project supports Vivado SDK and you want to jump directly in, otherwise select the “Vivado Block Design or HDL Only” option. Review the Supported Projects table above to determine if the Hardware Handoff option is available.

Vivado Block Design or HDL Only

2.1) Within the project folder there will be several subfolders named “hw_handoff”, “proj”, “src”, “repo”, and “sdk”. Go into the proj folder, right click the “create_project” file and select Properties. Highlight and copy the file's location.

2.2) Open Vivado and find the Tcl Console on the bottom of the window. Enter the letters 'cd' (change directory) followed by the file path you copied earlier.

Important

Select the proj folder from the drop-down menu to make sure that Vivado converts the path's back slashes ' / ' to forward slashes ' \ '. Vivado will not recognize the path otherwise.

2.3) Enter the command “source ./create_project.tcl”, this will set up the project for you within the proj directory you previously cd'd into.

2.4) The project will now be open in Vivado and you can navigate through the Design Sources subwindow or select Open Block Design in the project flow manager to the left to see how the project hardware works. (Not all projects will have a block design)

SDK Hardware Handoff

2.1) Find and Launch Vivado SDK.

2.2) In the Select Workspace dialog, click Browse, then find and select the “sdk” directory of your project.

2.3) Click Ok to finish launching Vivado SDK.

2.4) In the main page that pops up, click the Import Projects button.

2.5) Check the Select root directory option, then click Browse, again find and select the “sdk” directory.

2.6) Make sure that the hw_handoff, application, and application board support package (BSP) project are all checked, then click Finish to pull the projects into SDK.

TIP

Some common issues at this stage can be solved by right clicking the BSP project and selecting Regenerate BSP Sources.

The options in this step carry through from step 2. If you chose SDK Hardware Handoff before, select that again, otherwise, select the option that applies to the project you are working with. Review the Supported Projects table to help determine what kind of project you are working with.

HDL Only

3.1) Click Generate Bitstream on the left hand menu towards the bottom. In the “Launch Runs” dialog, make sure Launch runs on local host is selected and click OK. In the “No Implementation Results Available” dialog, click Yes to run synthesis and implementation.

Tip

If your computer has multiple cores, you can increase the number of jobs to make this process faster.

3.2) When this process has finished, which may take a while, in the “Bitstream Generation Completed” dialog, select Open Hardware Manager and click OK. Other interesting options here include “Open Implemented Design” which will show how your project logic will be placed on the FPGA. “View Reports” will show a number of different statistics about your project, including how well it meets timing requirements and what resources of your board will be used.

3.3) After the last step, if you don't have the hardware manager opened, select Hardware Manager from the Program and Debug section of the Flow Navigator to the left, just underneath Generate Bitstream.

3.4) Select Open Target from the green bar at the top. In the drop down menu that this creates, select Open New Target.

3.5) Click Next. Then make sure that Local server is selected in the “Connect to” drop down. Connect your board to your computer with a JTAG USB cable, then click Next.

3.6) Click Next and click Finish.

Important

The project may have further setup requirements, such as connecting a serial terminal to your board, visit it's wiki page to make sure.

3.7) Select Program Device from the green bar, then select your device from the dropdown list (there will usually only be one device listed). Then click Program.

Important

If nothing shows up in the “Bitstream file” text box, click the … button to the right, navigate to “proj