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playground:vivado_github_demo_startup_rework [2017/05/08 21:46] – Arthur Brown | playground:vivado_github_demo_startup_rework [2022/03/04 20:49] (current) – redirected to offical page James Colvin | ||
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- | ====== Using Github | + | ====== Using Digilent |
- | ===== Overview ===== | + | |
- | Digilent provides several projects through Github that are designed to demonstrate different uses of our FPGA and Zynq boards. This guide will describe how to download and use these projects. | + | |
- | At the end of this tutorial you will have your demo project running on your board. | + | ~~REDIRECT> |
- | ----- | + | ~~NOSEMANTIC~~ |
- | ===== Prerequisites ===== | + | {{tag>redirect}} |
- | + | ||
- | === Hardware === | + | |
- | * **A Supported Digilent 7-Series FPGA or Zynq Board** | + | |
- | * **USB Cables** | + | |
- | + | ||
- | === Software === | + | |
- | * **Xilinx Vivado 2016.X** | + | |
- | * //Vivado 2016.4 is used in this tutorial// | + | |
- | * **Digilent Board Support Files** | + | |
- | * //Follow the **[[vivado: | + | |
- | + | ||
- | + | ||
- | --> Projects Supported by this Tutorial# | + | |
- | + | ||
- | ^ Platform ^ Project Name ^ Uses SDK ^ Hardware Handoff Available ^ Wiki Link ^ Github Link ^ | + | |
- | | Arty | Pmod VGA Demo | No | No | [[https:// | + | |
- | + | ||
- | <-- | + | |
- | + | ||
- | + | ||
- | + | ||
- | <WRAP round important 660px> | + | |
- | ===Important=== | + | |
- | For further requirements, | + | |
- | </ | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | + | ||
- | =====Tutorial===== | + | |
- | + | ||
- | ====1. Download the Project ZIP from the Digilent Github ==== | + | |
- | + | ||
- | >1.1) From the demo repository landing page, select the **release** link. | + | |
- | > | + | |
- | >{{: | + | |
- | + | ||
- | >1.2) If the repository has multiple releases, select **Latest Release**, then click on the project ZIP file included in the Downloads section of the release to download it. | + | |
- | > | + | |
- | >< | + | |
- | ===Important=== | + | |
- | Make sure that you download the project-2016.4-x.zip, | + | |
- | </ | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >1.3) All of the necessary files are included within each project folder, with relative file paths established, | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====2. Find the Location of the Tcl Script ==== | + | |
- | + | ||
- | >Within the project folder there will be several subfolders named " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | FIXME proj should contain release.py script | + | |
- | + | ||
- | ====3. Create the Project in Vivado ==== | + | |
- | + | ||
- | >3.1) Open Vivado and find the Tcl Console on the bottom of the window. Enter the letters ' | + | |
- | > | + | |
- | >< | + | |
- | ===Important=== | + | |
- | Select the proj folder from the drop-down menu to make sure that Vivado converts the path's back slashes ' / ' to forward slashes ' \ '. Vivado will not recognize the path otherwise. | + | |
- | </ | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >3.2) Enter the command " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >3.3) The project will now be open in Vivado and you can navigate through the **Design Sources** subwindow or select **Open Block Design** in the project flow manager to the left to see how the project hardware works. (Not all projects will have a block design) | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====4. Compile, Program, and Run the Project ==== | + | |
- | + | ||
- | The remainder of this tutorial heavily depends on the type of project you are using. If your project does not use SDK, select the HDL Only option. If your project has a hardware handoff file and you don't wish to eventually make changes to the hardware design, select the SDK Hardware Handoff option. Otherwise, select the SDK and Block Design option. | + | |
- | + | ||
- | --> HDL Only# | + | |
- | + | ||
- | >4.1) Click **Generate Bitstream** on the left hand menu towards the bottom. In the " | + | |
- | > | + | |
- | >< | + | |
- | ===Tip=== | + | |
- | If your computer has multiple cores, you can increase the number of jobs to make this process faster. | + | |
- | </ | + | |
- | > | + | |
- | + | ||
- | >4.2) When this process has finished, which may take a while, in the " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.3) After the last step, if you don't have the hardware manager opened, select **Hardware Manager** from the Program and Debug section of the Flow Navigator to the left, just underneath **Generate Bitstream**. | + | |
- | + | ||
- | >4.4) Select **Open Target** from the green bar at the top. In the drop down menu that this creates, select **Open New Target**. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.5) Click **Next**. Then make sure that **Local server** is selected in the " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.6) Click **Next** and click **Finish**. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.7) Select **Program Device** from the green bar, then select your device from the dropdown list (there will usually only be one device listed). | + | |
- | > | + | |
- | >< | + | |
- | ===Important=== | + | |
- | If nothing shows up in the " | + | |
- | </ | + | |
- | > | + | |
- | + | ||
- | >The project will now be programmed onto your board and you can return to the project' | + | |
- | + | ||
- | <-- | + | |
- | + | ||
- | --> SDK Hardware Handoff# | + | |
- | + | ||
- | >4.1) From the File Dropdown select Launch SDK. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.2) In the Launch SDK prompt, click the **Exported location** dropdown, select **Choose location** and navigate and select the " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >< | + | |
- | ===Tip=== | + | |
- | If you get the warning " | + | |
- | </ | + | |
- | + | ||
- | >4.3) After plugging your board into your PC with a USB cable, select **Program FPGA** from the Xilinx Tools dropdown in the toolbar. Then click **Program**. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.4) Right click on the application project - the one that doesn' | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >The project will now be programmed onto your board and you can return to the project' | + | |
- | + | ||
- | <-- | + | |
- | + | ||
- | --> SDK and Block Design# | + | |
- | + | ||
- | >4.1) Generate Bitstream | + | |
- | + | ||
- | >4.2) Export Hardware - Include Bitsream | + | |
- | + | ||
- | >4.3) Launch SDK | + | |
- | + | ||
- | >4.3) | + | |
- | + | ||
- | >4.4) Export Hardware | + | |
- | + | ||
- | >4.5) Launch SDK | + | |
- | + | ||
- | + | ||
- | >< | + | |
- | ===Tip=== | + | |
- | If you get the warning " | + | |
- | </ | + | |
- | + | ||
- | >4.3) After plugging your board into your computer with a JTAG USB cable, select **Program FPGA** from the Xilinx Tools dropdown in the toolbar. Then click **Program**. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >4.4) Right click on the application project - the one that doesn' | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >The project will now be programmed onto your board and you can return to the project' | + | |
- | + | ||
- | + | ||
- | <-- | + | |
- | + | ||
- | ----- | + | |