Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
playground:vivado_github_demo_startup_rework [2017/05/05 19:40] – [2. Find the Location of the TCL Script] Arthur Brown | playground:vivado_github_demo_startup_rework [2022/03/04 20:49] (current) – redirected to offical page James Colvin | ||
---|---|---|---|
Line 1: | Line 1: | ||
- | ====== Using Github | + | ====== Using Digilent |
- | ===== Overview ===== | + | |
- | Digilent provides several projects through Github that are designed to demonstrate different usages of our FPGA and Zynq boards. This guide will describe how to download and use any of these projects. | + | |
- | At the end of this tutorial you will have your demo project running on your board. | + | ~~REDIRECT> |
- | ----- | + | ~~NOSEMANTIC~~ |
- | ===== Prerequisites ===== | + | {{tag>redirect}} |
- | + | ||
- | === Hardware === | + | |
- | * **A Supported Digilent 7-Series FPGA or Zynq Board** | + | |
- | * **USB Cables** | + | |
- | + | ||
- | === Software === | + | |
- | * **Xilinx Vivado 2016.X** | + | |
- | * //Vivado 2016.4 is used in this tutorial// | + | |
- | * **Digilent Board Support Files** | + | |
- | * //Follow the **[[vivado: | + | |
- | + | ||
- | + | ||
- | --> Projects Supported by this Tutorial# | + | |
- | + | ||
- | ^ Platform ^ Project Name ^ Uses SDK ^ Wiki Link ^ Github Link ^ | + | |
- | | Arty | Pmod VGA Demo | No | [[https:// | + | |
- | + | ||
- | <-- | + | |
- | + | ||
- | + | ||
- | + | ||
- | <WRAP round important 660px> | + | |
- | ===Important=== | + | |
- | For further requirements, | + | |
- | </ | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | + | ||
- | =====Tutorial===== | + | |
- | + | ||
- | ====1. Download the Project ZIP from the Digilent Github ==== | + | |
- | >1.1) From the demo repository landing page, select the **release** link. | + | |
- | > | + | |
- | >{{: | + | |
- | + | ||
- | >1.2) If the repository has multiple releases, select **Latest Release**, then click on the project ZIP file included in the Downloads section of the release to download it. | + | |
- | > | + | |
- | >< | + | |
- | ===Important=== | + | |
- | Make sure that you download the project-version.zip, | + | |
- | </ | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >1.3) All of the necessary files are included within each project folder, with relative file paths established, | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====2. Find the Location of the Tcl Script ==== | + | |
- | >Within the project folder there will be several subfolders named " | + | |
- | > | + | |
- | > | + | |
- | ====3. Create the Project in Vivado ==== | + | |
- | >3.1) Open Vivado 2016.4 and select the Tcl Console. | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | >3.2) Open Vivado and find the Tcl Console on the bottom of the window. Enter the letters ' | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | + | ||
- | >3.3) Enter the command " | + | |
- | + | ||
- | >3.4) The project will now be open in Vivado and you can navigate through the the Design Sources or Open the Block Design (if they exist) to understand how the project fits together. | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====4. Generate a Bitstream ==== | + | |
- | + | ||
- | >4.1) Click **Generate Bitstream** on the left hand menu towards the bottom. In the " | + | |
- | > | + | |
- | >< | + | |
- | ===Tip=== | + | |
- | If your computer has multiple cores, you can increase the number of jobs to make this process faster. | + | |
- | </ | + | |
- | > | + | |
- | + | ||
- | >4.2) When this process has finished, which may take a while, in the " | + | |
- | > | + | |
- | > | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====5. Program your FPGA or Zynq ==== | + | |
- | + | ||
- | >5.1) Open Hardware Manager | + | |
- | + | ||
- | >5.2) Open New Target | + | |
- | + | ||
- | >5.3) Local Server | + | |
- | + | ||
- | >5.4) Finish | + | |
- | + | ||
- | >5.5) Program Device | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | /* end if */ | + | |
- | + | ||
- | /* if sdk */ | + | |
- | + | ||
- | ====5. Launch Vivado SDK ==== | + | |
- | + | ||
- | >Export Hardware - Include Bitsream | + | |
- | + | ||
- | >Launch SDK | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====6. Compile ==== | + | |
- | + | ||
- | > | + | |
- | + | ||
- | >Build All | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====7. Program the FPGA or Zynq PL ==== | + | |
- | + | ||
- | >Make sure that your board is turned on and connected to the host PC via both the JTAG USB port and the UART USB port. | + | |
- | + | ||
- | >On the top toolbar, click the Program FPGA button. | + | |
- | + | ||
- | >Click Program to program your FPGA with your hardware design. | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | ====7. Program the Processor ==== | + | |
- | + | ||
- | >Select your Pmods project and click the Run As… button. Select Launch on Hardware (System Debugger) and click OK. | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | /* end if */ | + | |
- | + | ||
- | + | ||
- | + | ||
- | + | ||
- | --> Test# | + | |
- | + | ||
- | <WRAP round important 660px> | + | |
- | ===Important=== | + | |
- | Important thing here. | + | |
- | </ | + | |
- | + | ||
- | <WRAP round tip 650px> | + | |
- | ===Tip=== | + | |
- | Use a tip box for tips. | + | |
- | </ | + | |
- | + | ||
- | <-- | + | |