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playground:vivado_github_demo_startup_rework [2017/05/05 17:40] – [4. Generate a Bitstream] Arthur Brownplayground:vivado_github_demo_startup_rework [2022/03/04 20:49] (current) – redirected to offical page James Colvin
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-====== Using Github Demos ====== +====== Using Digilent Github Demo Projects (REDIRECT) ======
-===== Overview ===== +
-Digilent provides several projects through Github that are designed to demonstrate different usages of our FPGA and Zynq boards. This guide will describe how to download and use any of these projects. +
  
-At the end of this tutorial you will have your demo project running on your board.+~~REDIRECT>learn/programmable-logic/tutorials/github-demos/start~~
  
------+~~NOSEMANTIC~~
  
-===== Prerequisites ===== +{{tag>redirect}}
- +
-=== Hardware === +
-  * **A Supported Digilent 7-Series FPGA or Zynq Board** +
-  * **USB Cables** +
- +
-=== Software === +
-  * **Xilinx Vivado 2016.X** +
-    * //Vivado 2016.4 is used in this tutorial// +
-  * **Digilent Board Support Files** +
-    * //Follow the **[[vivado:boardfiles|wiki guide]]** on how to install Board Support Files for Vivado 2015.X// +
- +
- +
---> Projects Supported by this Tutorial# +
- +
-^ Platform ^ Project Name  ^ Uses SDK ^ Wiki Link ^ Github Link ^ +
-| Arty     | Pmod VGA Demo | No       | [[https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-pmod-vga-demo/start|Internal Link]] | [[https://github.com/Digilent/Arty-Pmod-VGA|External Link]] | +
- +
-<-- +
- +
- +
- +
-<WRAP round important 660px>  +
-===Important=== +
-For further requirements, please review the project's wiki page . +
-</WRAP> +
- +
------ +
- +
- +
-=====Tutorial===== +
- +
-====1. Download the Project ZIP from the Digilent Github ==== +
->1.1) From the demo repository landing page, select the **release** link. +
-> +
->{{:playground:clickrelease.jpg?600|}} +
- +
->1.2) Select **Latest Release**, then click on the project ZIP file included in the Downloads section of the release to download. +
-> +
-><WRAP round important 660px>  +
-===Important=== +
-Make sure that you download the project-version.zip, not the source code archive. +
-</WRAP> +
-> +
->{{:playground:downloadzip.jpg?600|}} +
- +
->1.3) All of the necessary files are included within each project folder, with relative file paths established, so as long as the files aren't moved around within the folder, you can move and run the project from any location. +
- +
------ +
- +
-====2. Find the Location of the TCL Script ==== +
-Within the project folder there will be several subfolders named "hw_handoff", "proj", "src", "repo", and "sdk". +
-Go into the proj folder, right click the “create_project” file and select “Properties”. +
-Highlight and copy the file's location. +
- +
-====3. Create the Project in Vivado ==== +
->3.1) Open Vivado 2016.4 and select the TCL Console. +
-> +
->{{:playground:cd.jpg?400|}} +
- +
->3.2) Open Vivado and find the Tcl Console on the bottom of the window. Enter the letters 'cd' (change directory) followed by the file path you copied earlier. +
-> +
->{{:playground:fullcd.jpg?600|}} +
- +
- +
->3.3) Enter the command "source ./create_project.tcl" +
- +
->3.4) The project will now be open in Vivado and you can navigate through the the Design Sources or Open the Block Design (if they exist) to understand how the project fits together. +
- +
------ +
- +
-====4. Generate a Bitstream ==== +
- +
->4.1) Click **Generate Bitstream** on the left hand menu towards the bottom. +
- +
->4.2) For the pop up "No Implementation Results Available", click **Yes** to run synthesis and implementation. +
- +
->4.3) Vivado will run through both Run Synthesis and Run Implementation before it generates the bitstream automatically. +
- +
->4.4) When Bitstream Generation has completed, Select **Open Hardware Manager** and click **OK**. The other options here will let you "Open Implemented Design", to view how your project logic will be placed on the FPGA. "View Reports" will show a number of different statistics about your project, including how well it fits timing requirements and what resources of your board will be used. +
- +
------ +
- +
-/* if no sdk */ +
- +
-====5. Program your FPGA or Zynq ==== +
- +
->5.1) Open Hardware Manager +
- +
->5.2) Open New Target +
- +
->5.3) Local Server +
- +
->5.4) Finish +
- +
->5.5) Program Device +
- +
------ +
- +
-/* end if */ +
- +
-/* if sdk */ +
- +
-====5. Launch Vivado SDK ==== +
- +
->Export Hardware - Include Bitsream +
- +
->Launch SDK +
- +
------ +
- +
-====6. Compile ==== +
- +
->Import? +
- +
->Build All +
- +
------ +
- +
-====7. Program the FPGA or Zynq PL ==== +
- +
->Make sure that your board is turned on and connected to the host PC via both the JTAG USB port and the UART USB port. +
- +
->On the top toolbar, click the  Program FPGA button. +
- +
->Click Program to program your FPGA with your hardware design. +
- +
------ +
- +
-====7. Program the Processor ==== +
- +
->Select your Pmods project and click the  Run As… button. Select Launch on Hardware (System Debugger) and click OK. +
- +
------ +
- +
-/* end if */ +
- +
- +
- +
- +
---> Test# +
- +
-<WRAP round important 660px>  +
-===Important=== +
-Important thing here. +
-</WRAP> +
- +
-<WRAP round tip 650px>  +
-===Tip=== +
-Use a tip box for tips. +
-</WRAP> +
- +
-<--+