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playground:tab_5_mb_mig [2017/01/31 02:49] – created sbobrowiczplayground:tab_5_mb_mig [2023/02/13 05:20] (current) – Scandiweb
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 >5.1) The PmodOLEDrgb requires a 50MHz ext_spi_clk, so we must generate this clock from the MIG (in a Microblaze design) or from the Zynq processor(in a Zynq design). >5.1) The PmodOLEDrgb requires a 50MHz ext_spi_clk, so we must generate this clock from the MIG (in a Microblaze design) or from the Zynq processor(in a Zynq design).
 >**Microblaze**: Double click the mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clicking **Next** until you see **Select Additional Clocks** (shown below). Click this box and select a 50MHz or less clock from the drop down list. >**Microblaze**: Double click the mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clicking **Next** until you see **Select Additional Clocks** (shown below). Click this box and select a 50MHz or less clock from the drop down list.